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Now showing items 49 - 64 of 86

  • A Self-compensation OCP Control Scheme for Primary-side Controlled Flyback AC/DC Converters

    Zhu, Zhangming   Wu, Qiang   Wang, Zeyu  

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  • Ultrawideband Power-Switchable Transmitter With 17.7-dBm Output Power for See-Through-Wall Radar

    Liu, Maliang   Xiao, Jinhai   Luo, Peng   Zhu, Zhangming   Yang, Yintang  

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  • High Input Impedance Low-Noise CMOS Analog Frontend IC for Wearable Electrocardiogram Monitoring

    Zhang, Chenggao   Wang, Jingyu   Wang, Ling   Liu, Lianxi   Li, Yani   Zhu, Zhangming  

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  • A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier

    Liu, Shubin   Han, Haolin   Shen, Yi   Zhu, Zhangming  

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  • A low cross-regulation and high-efficiency SIDO boost converter with near-threshold start-up

    Liu, Lianxi   Chen, Cheng   Liao, Xufeng   Huang, Wenbin   Mu, Junchao   Zhu, Zhangming  

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  • Energy-efficient and two-step structure switching scheme based on reference-free for SAR ADC

    Ding, Ruixue   Dong, Shaopeng   Sun, Depeng   Liu, Shubin   Zhu, Zhangming  

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  • A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS

    Zhang, Liang   Li, Dengquan   Zhu, Zhangming   Yang, Yintang  

    This paper presents a 10-GS/s 6-bit track-and-hold amplifier (THA), which is designed for a 16 way time-interleaved successive approximation register (SAR) analog to digital converter (ADC). To extend the bandwidth, a differential source-degenerated common-source amplifier with peaking inductance is adopted as an input buffer. A switched source follower master track and-hold stage samples the 800-mV(PP) differential input signal at 10 GHz. Moreover, the THA cancels the feed-through in hold mode by a clock-controlled transistor. The proposed THA is simulated in 65-nm CMOS technology. It operates with 1.8/1.2-V supply and consumes 84.8 mW. At a sampling rate of 10 GS/s, -41-dB total harmonic distortion (THD) is achieved with input frequencies up to 5 GHz.
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  • An Effective Approach of Reducing the Keep-Out-Zone Induced by Coaxial Through-Silicon-Via

    Wang, Fengjuan   Zhu, Zhangming   Yang, Yintang   Yin, Xiangkun   Liu, Xiaoxian   Ding, Ruixue  

    Keep-out-zone (KOZ) is a conservative way to prevent any devices/cells from being impacted by the through-silicon-via (TSV)-induced stress. In this paper, an effective approach was proposed of reducing the KOZ induced by coaxial TSV, by using the structure of coaxial-annular TSV, without decreasing the electrical performance of coaxial TSV. The analytical model was developed appropriate for the thermal stress induced by both coaxial and coaxial-annular TSVs, and was verified by the finite element method. The KOZs induced by coaxial and coaxial-annular TSVs were compared in detail, and the effects of Cu plasticity, TSV material, TSV size, and inner metal plating ratio of coaxial-annular TSV were also studied. The electrical characteristics of different TSVs were compared by employing ANSYS' HFSS, and a feasible fabrication process for coaxial-annular TSV was suggested. It could be concluded that: 1) a 1.6-mu m (22.2%) drop of KOZ for coaxial-annular TSV could be reached as compared with that of coaxial TSV; 2) coaxial-annular TSV was proved to offer the same superior signal integrity with coaxial TSV, improving S21 by about 93% at 5 GHz and 60% at 20 GHz compared with ordinary cylindrical and annular TSVs; and 3) the coaxial-annular TSV is realizable.
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  • A 92.1% area-efficient charge sharing switching scheme with near zero reset energy for SAR ADCs

    Yue, Peiyi   Zhang, Yanbo   Li, Yongyuan   Zhu, Zhangming  

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  • Electrical models of through silicon Vias and silicon-based devices for millimeter-wave application

    Liu, Xiaoxian   Zhu, Zhangming   Yang, Yintang   Liu, Yang   Lu, Qijun   Yin, Xiangkun  

    As the short vertical interconnections can significantly shorten the interconnect length between different circuits, three-dimensional integrated circuits (3D ICs) based on the through-silicon via (TSV) technology are considered as one of the most promising alternatives to overcome the scaling limits of Moore's low. Moreover, as the silicon technologies have been progressively expanded into the millimeter-wave (mmW) realm, the TSV technology also provides a promising option to realize a compact system with high performance and operating frequencies. This article provides an overview of recent advances in the development of TSV technologies and silicon-based passive devices for mmW applications. As various kinds of TSV losses are detrimental to the electrical performance of 3D ICs, especially in mmW systems, TSVs exploiting novel structures and materials still needs much more research, making it possible to integrate the passive device on 3D ICs and providing a promising option to realize a compact mmW system with excellent electrical performance and system reliability.
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  • A 1.33 mu W 10-bit 200KS/s SAR ADC with a tri-level based capacitor switching procedure

    Zhu, Zhangming   Xiao, Yu   Wang, Weitie   Guan, Yuheng   Liu, Lianxi   Yang, Yintang  

    A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) using an energy-efficient tri-level based capacitor switching procedure is presented. The proposed switching procedure achieves 97.66% less switching energy when compared to the conventional method. The number of unit capacitors is reduced by a factor of 4 over that of conventional architecture as well. To make the power consumption of the comparator scale down with respect to the comparison rate, the fully dynamic comparator is used. Moreover, the dynamic logic circuit is implemented to further reduce the power of digital circuits. The ADC is implemented in a 0.18 mu m 1P6M CMOS technology. At 1.0-V power supply and 200KS/s, the ADC achieves an SNDR of 60.54 dB and consumes 1.33 mu W, resulting in a figure-of-merit (FOM) of 7.7 fJ/conversion-step. The ADC core occupies an active area of only 230 x 400 mu m(2). 2013 Elsevier Ltd. All rights reserved.
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  • Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits

    Qian, Libo   Zhu, Zhangming   Yang, Yintang  

    Through-silicon-via (TSV) interconnect is one of the main technologies for three-dimensional integrated circuits production (3-D ICs). Based on a parasitic parameters extraction model, first order expressions for the TSV resistances, inductances, and capacitance as functions of physical dimension and material characteristic are derived. Analyzing the impact of TSV size and placement on the interconnect timing performance and signal integrity, this paper presents an approach for TSV insertion in 3D ICs to minimize the propagation delay with consideration to signal reflection. Simulation results in multiple heterogeneous 3D architectures demonstrate that our approach in generally can result in a 49.96% improvement in average delay, a 62.28% decrease in the reflection coefficient, and the optimization for delay can be more effective for higher non-uniform inter-plane interconnects. The proposed approach can be integrated into the TSV-aware design and optimization tools for 3-D circuits to enhance system performance. (C) 2011 Elsevier Ltd. All rights reserved.
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  • Temperature-dependent characterizations on parasitic capacitance of tapered through silicon via (T-TSV)

    Liu, Yang   Zhu, Zhangming   Liu, Xiaoxian   Gu, Huaxi   Guo, Lixin  

    With increasing integration density of three-dimensional ICs, temperature is one of the major concern of circuit design, which influences the performance and reliability. In this paper, the parasitic capacitance of tapered TSV (T-TSV) with respect of thermal properties is studied. The concept of the Temperature Coefficient of Capacitance (TCC) is proposed to model the sensitive of TSV capacitance to temperature. It is found that TSV capacitance is sensitive to temperature under high frequency application, and the MOS capacitance variation is the main reason for the change of TSV capacitance and the TCC increases with elevated temperature. Furthermore, the affection of TSV dimensions on TCC arc discussed. It is shown that the TCC increases gradually as the TSV radius increases, while the thickness of dielectric layer is the opposite. The cylinder TSV is less thermal sensitive than tapered TSV. This paper provides basis for TSV design considering the temperature effect.
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  • A 1.2 V,3.0 ppm/degrees C,3.6 mu A CMOS bandgap reference with novel 3-order curvature compensation

    Liu, Lianxi   Huang, Wenbin   Mu, Junchao   Zhu, Zhangming   Yang, Yintang  

    This paper presents a bandgap reference with a high-order curvature compensation circuit which can improve the temperature coefficient (TC) in a wide temperature range. The proposed compensation circuit includes a second-order and a third-order curvature current generators as well as an I-V converter. These two curvature currents are achieved by utilizing the exponential behavior of sub-threshold MOSFET and used for compensating the high-order temperature dependence of BJT base-emitter voltage via I-V converter. The proposed BGR is implemented in a CMOS 0.18 mu m process with the active area of 0.056 mm(2). Measurements on ten samples showed that at the minimum supply voltage 1.2 V, the TC varies from 1.7 to 6.9 ppm/degrees C over a temperature range of 170 degrees C (-45 degrees C-125 degrees C) with an average value of 3.0 ppm/degrees C and the total current consumption of 3.6 mu A at room temperature. In the supply voltage range of 1.2-1.8 V, the line regulation (LR) is 0.025%/V.
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  • An Improved-Linearity,Single-Stage Variable-Gain Amplifier Using Current Squarer for Wider Gain Range

    Wang, Jingyu   Zhu, Zhangming  

    A novel single-stage variable-gain amplifier (VGA) based on transconductance -ratio amplifier is analyzed and designed with wider linear-in-dB gain range and improved linearity. The variable-gain amplifier proposed here consists of an exponential control block, a current squarer and an amplifier block with both input and load degeneration. With the help of current squarer which gets square function of the output current from exponential control block, the VGA achieves the maximum linear gain range in single stage. Current squarer is proposed, which is designed with compensation technique to minimize the second-order effect caused by carrier mobility reduction in short channel MOSFET. To avoid the poor linearity performance of the -ratio amplifiers, the distortion is analyzed and the linearity is improved by applying input and load degenerating technique. At the same power consumption, the input 1 dB compression point can be improved by nearly 8.78 dB. Simulation results show that the VGA can provide a gain variation range of 64.09 dB (from to 28.5 dB) with a 3-dB bandwidth from 47 to 640 MHz. The circuit consumes the maximum power 3.5 mW from a 1.8-V supply.
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  • A low-power low-noise amplifier with fully self-biased feedback loop structure for neural recording

    Zhang, Xianzhe   Wang, Jingyu   Zhu, Zhangming  

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