A low-power low-supply high-LR high-PSR MOSFET-only voltage reference is proposed in this paper. The proposed voltage reference is designed in the standard 0.18 mu m CMOS process. In the typical case, when the temperature sweeps from -20 degrees C to 80 degrees C, the simulation result shows that the proposed voltage reference achieves a temperature coefficient of 25 ppm/degrees C. And the line regulation is as high as 0.067%/V, at room temperature. At the low frequency (< 100 Hz), a PSR of 44 dB is obtained. The reference succeeds in working at the supply voltage as low as 0.6 V, with the power consumption being 31nW. The proposed voltage reference occupies an area of 130 mu m x55 mu m.
Threshold voltage self-compensation technology (TVSC) has been widely used in RF energy harvester. In this paper, the influence of the size of rectifying transistors, the stages and compensation orders of the rectifier, and the impedance matching network on the performance of RF energy harvester has been studied. A dual band RF energy harvester with hybrid threshold voltage self-compensation (HTVSC) is proposed in this paper in 65-nm CMOS process according to the distribution characteristic of the ambient RF energy. By combining TVSC and the technology of weak forward bias between the source and body of the rectifying transistor, the threshold voltage of MOSFET can be dramatically decreased. The performance of the RF energy harvester has been improved using this new technology. The simulation results show that the proposed dual band RF energy harvester can acquire energy at the band of 900 MHz and 2.4 GHz. At 900 MHz-band (825-960 MHz), with 1 M Omega load resistor, the output voltage of the energy harvester can be over 1.0V with a minimum -18 dBm RF input power and a maximum 13.8% power conversion efficiency (PCE). At 2.4 GHz-band (2.4-2.485 GHz), the minimum input power can be as low as -19 dBm with a maximum efficiency of 16.8%.
A novel bootstrapped switch scheme with low distortion and high-speed is presented. Transmission gate (TG) switch is used to implement the switch circuit, which results in a reduction in the effect of charge injection during sampling phase and an improved linearity. The parasitic capacitance connected to the top plate of battery capacitor is minimized for higher output voltage. The switch has been simulated in Spectre using an SMIC 0.18 mum CMOS technology at 3.3 V and been applied to a 4-bit multiplying DAC (MDAC) in a 14-bit 100 MS/s pipelined analog-to-digital converter (ADC). The 4-bit MDAC has shown a satisfying dynamic performance.
A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 mu m 3.3V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 mu W.
Based on TSMC 0.18 mu m 1.8V CMOS process, a low power 10-bit 200 KS/s successive approximation register (SAR) analog-to-digital (ADC) is realized. This paper mainly considers the improvement of linearity and the optimization of power consumption. And a novel switching sequence is proposed which allows both to achieve a better compromise. Moreover, the fully dynamic comparator, which consumes no static power, and the optimization of SAR control logic, further reduce power consumption. The simulation results show that at 1.0V supply and 200 KS/s, the ADC achieves an signal-to-noise and distortion-ration (SNDR) of 59.78 dB and consumes 3.03 mu W, resulting in a figure-of-merit (FOM) of 19.0 fJ/conversion-step. The ADC core occupies an active area of only 260 x 220 mu m(2).
Wang, Tao
Zhu, Zhangming
Zhang, Liang
Yang, Yintang
This paper presents an 8-bit 320 MS/s single-channel successive approximation register (SAR) analog-to-digital converter (ADC) with low power consumption. Through a procedure of splitting all the most significant bit (MSB) capacitors except the least significant bit (LSB) capacitor into two equal sub-capacitors and reusing the terminal capacitor, the average switching energy and total capacitance can be reduced by about 87 and 50% respectively compared to the conventional procedure. Meanwhile, high-speed operation can be achieved by using a novel SAR control logic featuring efficient hardware cost and small critical path delay. In addition, this paper analyzes how to obtain the value of the unit capacitance which exhibits trade-offs between conversion rate, power consumption and linearity performance. The SAR ADC is simulated in 65 nm CMOS technology. It can achieve 48.63 dB SNDR, 63.61 dB SFDR at a supply voltage of 1.2 V and sampling frequency of 320 MS/s for near-Nyquist input, consuming 2.59 mW of power and with a FoM of 37 fJ/conversion-step.
Li, Yani
Zhu, Zhangming
Yang, Yintang
Sun, Yadong
Wang, Xu
To improve conversion efficiency and output quality of the energy harvester, a novel interface circuit with composite maximum power point tracking (MPPT) in energy harvesting applications is proposed in this paper. By using the ultra-low-voltage multiplier with digital control and simple one-cycle variable frequency technique, the converter realizes fast power tracking and high conversion efficiency, and minimizes the power consumption and harmonics, thereby obtaining high tracking precise and low total harmonic distortion (THD). Implemented in 65-nm CMOS process, this converter achieves 85.9% peak power efficiency with dc output voltage of 1.6 V. The peak tracking efficiency and THD are 99.2% and 1.3%, respectively. The peak output power is 18.31 mu W, and the power loss of the entire converter is only 16.53 mu W.
An equivalent-circuit model of Cu-carbon nanotube heterogeneous coaxial through-silicon vias (HCTSVs) in 3-D integrated circuits (3-D ICs) is proposed in this paper. Based on the complex effective conductivity method, the resistances and inductances of Cu-single walled carbon nanotube (SWCNT) HCTSVs and Cu-multi walled carbon nanotube (MWCNT) HCTSVs are compared with that of Cu coaxial through-silicon vias (CTSVs). Furthermore, using the proposed model, the magnitudes of their insertion losses are compared. It is shown that the transmission performance of Cu-SWCNT HCTSVs with higher metallic fraction and Cu-MWCNT HCTSVs is better than that of Cu CTSVs, and the improvement of Cu-MWCNT HCTSVs is more obvious at high frequencies. Finally, the transmission characteristics of Cu-MWCNT HCTSVs are analyzed deeply to provide helpful design guidelines for them in future high-speed 3-D ICs.
With the application of the voltage divider to the traditional bandgap reference without resistors, a high precision CMOS voltage reference without resistors has been proposed. The temperature coefficient has improved because the divider introduces the temperature compensation. The output reference voltage is 410.39 mV at the room temperature. The temperature coefficient of the voltage reference is 3.02 ppm/degC in the range from -20degC to 120degC. Moreover, the power supply rejection ratio of the voltage reference is -52.6 dB and the power consumption is 5.61 muW.
With the application of the voltage divider to the traditional bandgap reference without resistors, a high precision CMOS voltage reference without resistors has been proposed. The temperature coefficient has improved because the divider introduces the temperature compensation. The output reference voltage is 410.39 mV at the room temperature. The temperature coefficient of the voltage reference is 3.02 ppm/degrees C in the range from -20 degrees C to 120 degrees C. Moreover, the power supply rejection ratio of the voltage reference is -52.6 dB and the power consumption is 5.61 mu W.