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Now showing items 1 - 16 of 281


    Provided is a Gm-C filter frequency-calibration circuit having low power consumption and high calibration precision; the frequency calibration circuit comprises four modules: a clock generation circuit, a sample-and-hold circuit, a master transconductance amplifier (Gm), and an error amplifier (OTA2). The master transconductance amplifier (Gm) in the master-slave structure control calibration circuit matches the slave transconductance amplifier in the Gm-C filter, and is controlled by the same bias voltage. The error of the frequency characteristics of the Gm-C filter is influenced primarily by such factors as the transconductance value of the transconductance amplifier, the process variation of the capacitance, and temperature; the consideration of the frequency characteristics of the Gm-C filter is determined primarily by the time constant Gm/C thereof; by means of converting the transconductance value Gm of the transconductance amplifier into a variable having an accurate directly proportional relationship with the capacitance C, the influence of the process variation of the capacitance on the time constant Gm/C is eliminated, allowing for very high calibration accuracy; the invention has the features of a simple structure, low power consumption, and a small chip area, and is also highly stable.
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    A band-gap reference voltage source with a high power supply rejection ratio comprises a voltage self-regulating circuit (1), a starting circuit (2), a first-order temperature compensation reference voltage generating circuit (3), an error amplifier (4), a bias voltage generating circuit (5), and a reference starting circuit (6). According to the band-gap reference voltage source, power supply noise is suppressed to a certain extent by using the voltage self-regulating circuit (1), and then power is supplied to a back-stage band-gap reference circuit, so that the band-gap reference circuit further suppress the noise, and the entire power source thus has a high power supply rejection ratio. In addition, the self-regulating circuit (1) further comprises a feedback loop, the magnitude of an output current can be automatically regulated, and the problem of instability of the entire circuit due to the fact that the current required by the back-stage circuit increases suddenly is solved; meanwhile, the power supply rejection ratio of the band-gap reference voltage source can further be improved; compared with a conventional band-gap reference voltage source, the present invention has better stability, a higher power supply rejection ratio, and can meet high-accuracy operating requirements.
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    An E-TSPC structure-based low-power-consumption 2/3 frequency divider circuit comprises a first-stage D trigger DFF1, a second-stage D trigger DFF2, and an inter-stage embedded gate circuit. A clock signal Clk serves as a clock signal to be subjected to frequency division, a positive clock signal Q and a negative clock signal QN serve as clock signals after the frequency division. A 2-frequency-division mode or a 3-frequency-division mode is selected by means of a mode control signal Mc: when the mode control signal Mc is at a low level, the frequency divider circuit works at the 3-frequency-division mode, and when the mode control signal input end Mc is at a high level, the frequency divider circuit works at the 2-frequency-division mode. Compared with a conventional frequency divider having a TSPC structure, the frequency division circuit has a higher working efficiency; and compared with a conventional 2/3 frequency division circuit having an E-TSPC structure, the frequency division circuit has lower power consumption, so that a very-low-power consumption 2/3 frequency division circuit capable of working at a gigahertz frequency is achieved.
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  • A Low Power Wide Tuning Range Two Stage Ring VCO with Frequency Enhancing

    Yan, Chenggang   Wu, Jianhui   Hu, Chen   Ji, Xincun  

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  • A low energy switching scheme for SAR ADC with MSB-splitting DAC structure

    Wang, Fufeng   Wu, Jianhui  

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    Disclosed is a fully-integrated anti-blocking radio frequency receiving front-end architecture, comprising a blocking signal filtering stage and a down mixing stage. The blocking signal filtering stage is a feed-forward structure, and a main branch and a feed-forward branch use low-noise amplifiers with same circuit structures to realize matching. In addition, the feed-forward branch uses the impedance moving feature of a passive mixer in the frequency domain, a band elimination filter is generated at a radio frequency local oscillator to filter useful signals, and then a useful radio frequency signal is obtained by subtracting an obtained blocking signal from a blocking signal of the main branch. Because the blocking signal is directly filtered out after two low-noise amplifiers, influence on another circuit is avoided, and other non-ideal factors are avoided. Down mixing is realized to obtain a useful middle-frequency signal by connecting the passive mixer.
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  • A Review on Calibration Methods of Timing-skew in Time-interleaved ADCs

    Li, Xin   Huang, Cheng   Ding, Desheng   Wu, Jianhui  

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  • Improved Adaptive Transform for Residue in H.264/AVC Lossless Video Coding

    Ou, Xianfeng   Zhang, Guoyun   Longyuan, Guo   Wu, Jianhui   Tu, Bing   Yang, Long  

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  • Improved single pass core design for high temperature Super LWR

    Wu, Jianhui   Oka, Yoshiaki  

    Core design of a supercritical-pressure light water cooled and moderated reactor (Super LWR) with single flow pass is carried out for achieving high outlet coolant temperature 500 degrees C and simplifying upper core structure. Both the coolant in water rod and fuel channel flows up and is mixed at the upper plenum. The structure inside pressure vessel is simplified as a PWR by eliminating upper core moderator distribution/guide tubes applied in previous two pass core. The fuel assemblies loaded at peripheral core region are divided into four flow zones by using separation plates to adjust flow to the power for increasing average outlet temperature. The shuffling scheme is carried out separately for inner and peripheral core assemblies. Axial fuel enrichment is split into four segments to control the axial power peaking due to relatively large axial water density variation. Five fuel batches are adopted to increase the discharge burn-up. The equilibrium core is analyzed by employing neutronic/thermal-hydraulic coupled calculation. The numerical results show that all the design criteria are fulfilled by the maximum cladding surface temperature of 656 degrees C with 500 degrees C average core outlet temperature, maximum linear heat generation rate of 37.4 kW/m and positive water density as well as shutdown margin of 1.45%dk/k. (C) 2013 Elsevier B.V. All rights reserved.
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  • Core design of super LWR with double tube water rods

    Wu, Jianhui   Oka, Yoshiaki  

    Double tube water rods are employed in core design of super LWR to simplify the upper core structure and refueling procedure. The light water moderator flows up in the inner tube from the bottom of the core, then, changes the flow direction at the top of the core into the outer tube and flows out at the bottom of the core. It eliminates the moderator guide/distribution tubes into the single tube water rods from the top dome of the reactor pressure vessel of the previous super LWR design. Two rows of fuel rods are filled between the water rods in the fuel assembly. Out-in refueling pattern is adopted to flatten radial power distribution. The peripheral fuel assemblies of the core are divided into four flow zones by separation plates for increasing the average core outlet temperature. Three enrichment zones are used for axial power flattening. The equilibrium core is analyzed based on neutronic/thermal-hydraulic coupled model. The results show that, by applying the separation plates in peripheral fuel assemblies and low gadolinia enrichment, the maximum cladding surface temperature (MCST) is limited to 653 degC with the average outlet temperature of 500 degC. The inherent safety is satisfied by the negative void reactivity effects and sufficient shutdown margin. [All rights reserved Elsevier].
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  • Flow effect on 135 I and 135 Xe evolution behavior in a molten salt reactor

    Wu, Jianhui   Guo, Chen   Cai, Xiangzhou   Yu, Chenggang   Zou, Chunyan   Han, Jianlong   Chen, Jingen  

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  • Subchannel analysis with turbulent mixing rate of supercritical pressure fluid

    Wu, Jianhui   Oka, Yoshiaki  

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    Disclosed in the present invention is an octapeptide of the formula Lys(AA-Asp-Gly-Arg)-Glu-Asp-Gly-modified dexamethasone, and AA in the octapeptide is L-Val or L-Phe. Also disclosed are the preparation method, nanostructure and use thereof. The octapeptide modified dexamethasone has an inhibitory effect on mouse retroauricular cardiac transplantation immunological rejection reactions, and has an inhibitory effect on inflammation caused by xylene.
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    An abrasive tool for conditioning CMP pads includes abrasive grains coupled to a substrate through a metal bond and a coating, e.g., a fluorine-doped nanocomposite coating. The abrasive grains can be arranged in a self-avoiding random distribution. In one implementation, an abrasive tool includes a coated plate and a coated abrasive article that has two abrading surfaces. Other implementations related to a process for producing an abrasive tool that includes a coating at one or more of its surfaces. Also described are methods for dressing a CMP pad.
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    Provided is a method for using a current DAC to eliminate DC offset in a variable-gain amplifier circuit; the differential input end of a variable-gain amplifier is shorted; the output signal of the variable-gain amplifier circuit is a DC offset voltage; an analog-to-digital converter is used to perform sampling detection and analog-to-digital conversion of the DC offset voltage, to obtain a digital value of the DC offset voltage; a modified bitwise comparison algorithm is used to process the DC offset voltage to obtain a control word for controlling a current DAC; finally, feedback correction is performed, by means of the current DAC, on the input end of the variable-gain amplifier, so as to eliminate the DC offset voltage. The method improves the conventional means of bitwise correction in digital auxiliary DC offset elimination technologies, and employs an analog-to-digital converter to directly detect the DC offset voltage, thus improving the speed of correction.
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    An automatic frequency band calibration method for rapid lock of a phase-locked loop system. An AFC module is used to calibrate the frequency band of a VCO, and automatically select a frequency band according to a target frequency point, thereby realizing rapid lock of a phase-locked loop. The method relates to using closed-loop calibration, controlling the hopping of the frequency dividing ratio of a frequency divider, locking Vctrl voltage using the phase-locked loop, sequentially obtaining a characteristic frequency dividing ratio of each frequency band to realize calibration of the corresponding characteristic frequency of each frequency band in an actual circuit, and storing characteristic frequency dividing ratio control words using a register. On the basis of the characteristic frequency dividing ratio result locked in the process, under a normal operation status, the outside provides a frequency dividing ratio corresponding to the target frequency point, the frequency band where the frequency point is located is automatically deduced, and a frequency band code is directly set to realize rapid lock of the phase-locked loop. The AFC algorithm provided by the method needs only a small number of registers to record and deduce calibration data of a larger number of frequency points, thereby saving resources and realizing rapid lock of the phase-locked loop.
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