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Now showing items 1 - 16 of 59

  • Hybrid CMOS/GaN 40-MHz Maximum 20-V Input DC-DC Multiphase Buck Converter

    Aklimi, Eyal   Piedra, Daniel   Tien, Kevin   Palacios, Tomas   Shepard, Kenneth L.  

    This paper presents a 40-MHz hybrid CMOS/GaN integrated multiphase dc-dc switched-inductor buck converter with a maximum 20-V input voltage. The half-bridge switches are realized using lateral AlGaN/GaN HEMTs, while the drivers and other circuitry are implemented in standard 180-nm CMOS. The interface between the CMOS and GaN dice is achieved through face-to-face bonding, reducing inductive parasitics for the connection to less than 15 pH. A capacitively coupled level shifter provides the gate drive for the high-side GaN switch using 5-V CMOS devices. The converter demonstrates 76% efficiency for 8: 1 V conversion and over 60% efficiency for conversion ratios up to 16: 1.
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  • A 20-V CMOS-Based Monolithic Bidirectional Power Switch

    Fu, Y.; Cheng, X.; Chen, Y.; Liou, J. J.; Shen, Z. J.  

    Bidirectional power-switching devices are needed in many power-management applications, particularly in lithium-ion battery protection circuitry. In this letter, a monolithic planar bidirectional power switch fabricated with a simplified CMOS technology is introduced. The new four-terminal device provides a blocking voltage greater than 20 V and a low on-resistance in either direction between its two power terminals. Detailed device characterization and analysis reveal that the new device structure has good latch-up immunity even though it comprises several p-n junctions in close proximity. This new CMOS-compatible power switch can be used in discrete form or as part of a power IC.
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  • Precise Measurement of a 20-V Programmable Josephson Voltage Standard System

    Yamada, Takahiro   Yamamori, Hirotake   Sasaki, Hitoshi   Shoji, Akira  

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  • 20V TO 50V HIGH CURRENT ASIC PIN DIODE DRIVER

    An apparatus having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to translate an input signal in a first voltage domain to generate a complementary pair of first signals in a second voltage domain. The second circuit may be configured to logically switch the first signals to generate a complementary pair of second signals in the second voltage domain. The first signals may be logically switched such that both of the second signals are inactive before one of the second signals transitions from inactive to active. The third circuit may be configured to amplify the second signals to generate a complementary pair of output signals in the second voltage domain. Each of the output signals generally has a current capacity to drive one or more of a plurality of diodes in a diode switch circuit.
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  • 20V to 50V high current ASIC PIN diode driver

    An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a plurality of second signals by a voltage translation of a plurality of first signals. The second circuit may be configured to switch the second signals to generate a plurality of third signals. The second signals are generally switched such that (i) all third signals are inactive before one of the third signals transitions from inactive to active while a switching condition is enabled and (ii) all third signals are switched inactive while the switching condition is disabled. The third circuit may be configured to amplify the third signals to generate a plurality of output signals. Each of the output signals generally has a current capacity to drive one or more of a plurality of diodes in a diode switch circuit.
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  • 20V to 50V high current ASIC PIN diode driver

    An apparatus having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to translate an input signal in a first voltage domain to generate a complementary pair of first signals in a second voltage domain. The second circuit may be configured to logically switch the first signals to generate a complementary pair of second signals in the second voltage domain. The first signals may be logically switched such that both of the second signals are inactive before one of the second signals transitions from inactive to active. The third circuit may be configured to amplify the second signals to generate a complementary pair of output signals in the second voltage domain. Each of the output signals generally has a current capacity to drive one or more of a plurality of diodes in a diode switch circuit.
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  • Precise Measurement of a 20-V Programmable Josephson Voltage Standard System

    Yamada, Takahiro   Yamamori, Hirotake   Sasaki, Hitoshi   Shoji, Akira  

    We demonstrated the precise measurement of a 20-V programmable Josephson voltage standard (PJVS) system with an accuracy of 10(-9). A 20-V PJVS chip including 524288 NbN/TiN(x)/NbN Josephson junctions (JJs) was used and operated in a cryocooler. By optimizing a microwave frequency, the widest current margin of a voltage step greater than 1 mA was obtained at 15.85 GHz. The maximum voltage of 17V was also obtained at 18.00 GHz although we could not obtain voltages exceeding 20V due to defective JJs. We also successfully compared the PJVS system with a 10-V Zener diode with an accuracy of 10(-8). (C) 2009 The Japan Society of Applied Physics
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  • 20V to 250V high current ASIC PIN diode driver

    An integrated circuit including a first circuit, a second circuit, a third circuit, a first complementary pair of transistors, and a second complementary pair of transistors. The first circuit may be configured to generate a first input signal in response to a first control input signal. The second circuit may be configured to generate a first output signal and a second output signal in response to the first input signal and a bias signal. The third circuit may be configured to generate the bias signal in response to a bias input signal. The first complementary pair of transistors may be configured to drive a first series output of the integrated circuit in response to the first output signal. The second complementary pair of transistors may be configured to drive a first shunt output of the integrated circuit in response to the second output signal.
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  • Hot-carrier reliability of 20V MOS transistors in 0.13 mu m CMOS technology

    Rey-Tauriac, Y   Badoc, J   Reynard, B   Bianchi, RA   Lachenal, D   Bravaix, A  

    This paper presents results of reliability investigation of 20V N-Drift MOS transistor in 0.13 mu m CMOS technology. Due to high performances required for CMOS applications, adding high voltage devices becomes a big challenge to guarantee the reliability criteria. In this context, new reliability approaches are needed. Safe Operating Area are defined for switch, V-ds limited and V-gs limited applications in order to improve circuit designs. For Vds limited applications, deep doping dose effects in drift area are investigated in correlation to lifetime evaluations based on device parameter shifts under hot carrier stressing. To further determine the amount and locations of hot carriers injections, accurate 2D technological and electrical simulations are performed and permit to select the best compromise between performance and reliability for N-Drift MOS transistor. (c) 2005 Elsevier Ltd. All rights reserved.
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  • Serrated yielding in the B2-ordered Nb–15Al–20V alloy

    T.S Rong  

    Serrated yielding is usually caused by the interaction of mobile dislocations with solute atoms or fine precipitates and the critical strain for commencing serration is a function of strain rate and temperature. However, serrated flow in the single B2 phase Nb-15Al-20V (atomic per cent) alloy is unusual. The serration occurs immediately after yielding over the whole range of strain rate from 10 -2 to 10 -4/s. In this paper, these serrations in flow stress are explained as a result of the interaction of planar slip systems. When a superdislocation sweeps across antiphase domain boundaries, additional antiphase boundary (APB) is left on the slip plane. An easy-slip channel is then created for the following superdislocations. Planar slip is thus preferred. If a planar slip band is intersected by another planar slip band, the existing planar slip channel will be destroyed. Superdislocations will then be temporarily trapped at the intersection. To maintain a constant strain rate, an increase of applied stress to release these trapped superdislocations by creating a new slip channel is therefore necessary. This repeated trapping and un-trapping of superdislocations leads to microstructural instability and serrated yielding
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  • Serrated yielding in the B2-ordered Nb–15Al–20V alloy

    Rong   T.S.  

    Serrated yielding is usually caused by the interaction of mobile dislocations with solute atoms or fine precipitates and the critical strain for commencing serration is a function of strain rate and temperature. However, serrated flow in the single B2 phase Nb–15Al–20V (atomic per cent) alloy is unusual. The serration occurs immediately after yielding over the whole range of strain rate from 10−2 to 10−4/s. In this paper, these serrations in flow stress are explained as a result of the interaction of planar slip systems. When a superdislocation sweeps across antiphase domain boundaries, additional antiphase boundary (APB) is left on the slip plane. An easy-slip channel is then created for the following superdislocations. Planar slip is thus preferred. If a planar slip band is intersected by another planar slip band, the existing planar slip channel will be destroyed. Superdislocations will then be temporarily trapped at the intersection. To maintain a constant strain rate, an increase of applied stress to release these trapped superdislocations by creating a new slip channel is therefore necessary. This repeated trapping and un-trapping of superdislocations leads to microstructural instability and serrated yielding.
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  • The feasibility of dynamic color separation: data from a 20V display prototype

    Clayton A. Washburn  

    This article provides performance requirements and measurement data on dynamic-color-separation (DCS) displays. Implementation for a 20 V prototype is described. Measurement on its electron gun and phosphor screen provides a benchmark by which requirements for the full range of color CRT displays may be extrapolated. The advantages of DCS are summarized
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  • The feasibility of dynamic color separation: data from a 20V display prototype

    Clayton A. Washburn  

    Abstract— This article provides performance requirements and measurement data on dynamic-color-separation (DCS) displays. Implementation for a 20V prototype is described. Measurement on its electron gun and phosphor screen provides a benchmark by which requirements for the full range of color CRT displays may be extrapolated. The advantages of DCS are summarized.
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  • Microstructure preparation and hot-deformation of Ti–46.2Al–2.0V–1.0Cr–0.5Ni alloy

    Ji Zhang   Zhihong Zhang   Xi Su   Dunxu Zou   Zengyong Zhong   Changhai Li  

    In this paper the near gamma microstructure with equiaxed fine grains was prepared in the cast Ti-46.2Al-2.0V-1.0Cr-0.5Ni alloy for the hot-compression tests. It has been found that the lamellar breakdown and segmental coarsening occurred when the cast lamellar microstructure was annealed at 1150degC. These degradation mechanisms resulted in the lamellar spheroidization and microstructure refinement in the studied alloy. This alloy with the prepared near gamma microstructure exhibited relatively good deformability at the temperatures below T e, such as keeping the soundness up to 150% true compressive strain and exhibiting rather low deformation resistance at the moderate strain rates in the isothermal hot-compression tests. Besides, the non-banded microstructure was observed in the deformed specimens
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  • Role of oxygen in stress-induced ω phase transformation and {332}〈113〉 mechanical twinning in βTi–20V alloy

    Wang, X.L.   Li, L.   Xing, H.   Ou, P.   Sun, J.  

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  • Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories

    YASUFUKU, Tadashi; ISHIDA, Koichi; MIYAMOTO, Shinji; NAKAI, Hiroto; TAKAMIYA, Makoto; SAKURAI, Takayasu; TAKEUCHI, Ken  

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