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Now showing items 1 - 11 of 11

  • PVT-Aware Design of Dopingless Dynamically Configurable Tunnel FET

    Lahgere, Avinash   Sahu, Chitrakant   Singh, Jawar  

    This paper presents a new design of dopingless dynamically configurable double-gate tunnel FET (TFET) for process-voltage-temperature (PVT)-aware applications. The dopingless FETs have recently been explored and showed very good electrostatic control over the channel with reduced thermal budget and process complexity. The proposed device makes use of the dopingless concept, but instead of charge plasma, electrostatic doping is used for carrier concentration under the source/drain region that allows dynamic configuration. The 2-D device simulation results show that the proposed device has promising switching behavior and offers significant reduction in PVT variations on different performance metrics, such as subthreshold swing and drive current as compared with a conventional TFET.
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  • PVT-Aware Design of Dopingless Dynamically Configurable Tunnel FET

    Lahgere, Avinash   Sahu, Chitrakant   Singh, Jawar  

    This paper presents a new design of dopingless dynamically configurable double-gate tunnel FET (TFET) for process-voltage-temperature (PVT)-aware applications. The dopingless FETs have recently been explored and showed very good electrostatic control over the channel with reduced thermal budget and process complexity. The proposed device makes use of the dopingless concept, but instead of charge plasma, electrostatic doping is used for carrier concentration under the source/drain region that allows dynamic configuration. The 2-D device simulation results show that the proposed device has promising switching behavior and offers significant reduction in PVT variations on different performance metrics, such as subthreshold swing and drive current as compared with a conventional TFET.
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  • 1-T Capacitorless DRAM Using Bandgap-Engineered Silicon-Germanium Bipolar I-MOS

    Lahgere, Avinash   Kumar, Mamidala Jagadesh  

    In this paper, a 1-Transitor (1-T) capacitorless dynamic random access memory (DRAM) using bandgap-engineered silicon-germanium Bipolar ionization metal oxide semiconductor field effect transistor (I-MOS) is investigated through numerical simulations. We have demonstrated the application of the proposed Si0.6Ge0.4 Bipolar I-MOS for realization of a 1-T capacitorless DRAM. The proposed device can achieve hysteresis at significantly lower drain voltages (V-LD =3D 0.45 V to V-LU =3D1.15 V), in comparison to the inversion mode device (V-LD =3D 8 V to V-LU =3D 11 V). In addition, the proposed 1-T capacitorless DRAM exhibits a wider hysteresis window (Delta V) of the order similar to 700 mV and a sensing margin (M) of similar to 5 orders in comparison to the inversion mode based 1-T capacitorless DRAM. Moreover, the proposed 1-T capacitorless DRAM exhibits the retention time of similar to 750 msec and similar to 320 msec for T =3D 25 degrees C and T =3D 85 degrees C, respectively. The proposed 1-T capacitorless DRAM also shows nondestructive read and an extreme long-term endurance. Therefore, the results presented in this paper can provide an opportunity for future DRAM design in deep nanometer technology.
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  • 1-T Capacitorless DRAM Using Bandgap-Engineered Silicon-Germanium Bipolar I-MOS

    Lahgere, Avinash   Kumar, Mamidala Jagadesh  

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  • A Tunnel Dielectric-Based Junctionless Transistor With Reduced Parasitic BJT Action

    Lahgere, Avinash   Kumar, Mamidala Jagadesh  

    In this paper, we demonstrate a tunnel dielectric-based junctionless transistor, referred as TD JLT, which consists of a thin dielectric layer in the middle of the channel region of a JLT leading to a drastically reduced parasitic bipolar junction transistor (BJT) action. Using calibrated 2-D simulations, we show that the proposed TD JLT has a significantly low off-state leakage current due to the presence of a tunneling barrier, and an enhanced sourceto- channel barrier height, which results in a diminished parasitic BJT action in the off-state. Further, the proposed TD JLT exhibits an extremely high I-ON/I-OFF ratio of similar to 1.1x10(7) for a channel length of 20 nm and a significant(I-ON/I-OFF) ratio of similar to 10(2) even for a channel length of 10 nm.
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  • A Tunnel Dielectric-Based Junctionless Transistor With Reduced Parasitic BJT Action

    Lahgere, Avinash   Kumar, Mamidala Jagadesh  

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  • The Charge Plasma n-p-n Impact Ionization MOS on FDSOI Technology:Proposal and Analysis

    Lahgere, Avinash   Kumar, Mamidala Jagadesh  

    In this paper, we propose the charge plasma n-p-n impact ionization MOS (I-MOS) on a lightly doped p-type silicon film using the charge plasma concept. The performance of the proposed device is exhaustively investigated using 2-D simulations. The proposed device does not have metallurgical junctions and needs no chemical doping for creating the source and drain regions. Therefore, the proposed device combines the benefits of the bipolar I-MOS (low avalanche breakdown voltage and immunity toward the hot carrier injection) and a junctionless FET (low thermal budget process). The proposed charge plasma n-p-n I-MOS exhibits excellent electrical characteristics, such as a low avalanche breakdown voltage (VB) of 2.123 V, a steep subthreshold swing of 4.53 mV/decade, and an I-ON/I-OFF ratio of similar to 10(6), as compared with the conventional bipolar I-MOS.
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  • The Charge Plasma n-p-n Impact Ionization MOS on FDSOI Technology: Proposal and Analysis

    Lahgere, Avinash   Kumar, Mamidala Jagadesh  

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  • Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs

    Lahgere, Avinash   Panchore, Meena   Singh, Jawar  

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  • 1-T Capacitorless DRAM Using Laterally Bandgap Engineered Si-Si:C Heterostructure Bipolar I-MOS for Improved Sensing Margin and Retention Time

    Lahgere, Avinash   Kumar, Mamidala Jagadesh  

    In this paper, a single transistor (1-T) capacitorless DRAMusing laterally bandgap engineered Si-Si:C heterostructure bipolar I-MOS is investigated using 2-D calibrated simulations. The proposed device features a high-K gate dielectric, a metal gate, and an epitaxially grown Si0.99C0.01 source/drain regions. Due to lattice mismatch between the Si: C source/drain and the Si channel and resultant strain effect, the proposed 1-T capacitorless DRAM memory cell exhibits enhanced memory characteristics, particularly the sensing margin and the retention time. The proposed 1-T capacitorless DRAM exhibits a sensing margin of the order of similar to 1.5 mu A/mu m and similar to 2.0 mu A/mu m for the temperatures T =3D 300 K and T =3D 358 K, respectively. Also, the proposed 1-T capacitorless DRAM memory cell shows a retention time of similar to 1.68 s and similar to 845 ms for T =3D 300 K and T =3D 358 K, respectively. Therefore, the proposed 1-T capacitorless memory has a greater potential to replace existing 1-T capacitorless DRAM memory.
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  • 1-T Capacitorless DRAM using Laterally Bandgap Engineered Si-Si:C Heterostructure Bipolar I-MOS for Improved Sensing Margin and Retention Time

    Lahgere, Avinash   Kumar, M.Jagadesh  

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