This brief presents the design of a novel low-electromagnetic interference DC-DC step-up (boost) switching converter for portable applications. The converter can switch between pulsewidth modulation and pulse-frequency modulation modes for different load conditions, and uses a new ultralow-current spread spectrum frequency modulator to reduce the harmonic noise peak. The stability of the converter system with a spread spectrum frequency modulator is first analyzed in this brief. The harmonic peak reduction for the switching frequency and the second harmonic is 14 and 18 dB, respectively. A new two-stage soft-start circuit is also implemented to greatly reduce the start-up current. The start-up current of the boost converter is effectively limited below 500 mA. This brief also investigates the effects of the spread spectrum on conversion efficiency and output ripple voltage. About 93% maximum conversion efficiency can be reached for both operation modes. The chip was fabricated using a TSMC 2P4M 0.35-mu m CMOS process.

This paper presents a digitally controlled way of generating the sinusoidal signal with less memory consumption. Moreover, this paper also presents a new switching frequency modulation technique. This technique utilizes the concept of spread spectrum frequency modulation that is used to suppress the electromagnetic interference (EMI) caused by high switching frequencies. Measurement results at the output sine pulse-width generation show that when the spread spectrum technique was applied to the conventional triangular wave and the fundamental, second, and third harmonics of switching frequency were reduced, respectively, by 12.8, 11.2, and 16.4 dB trading off with the slight increase in total harmonic distortion (THD) of 0.092% from a THD of 2.34%. While in the inverter output, there was a 14-dB reduction in EMI peak in exchange to 0.12% increase in THD from a THD of 2.57%.

A new PMOS backgate quadrature voltage controlled oscillator (QVCO) is designed and implemented using TSMC 0.18 mu m 1P6M CMOS technology. The phase noise of the PMOS hack-gate coupled QVCO operating at 1.5 V is measured to be -100 dBc/Hz and -125.08 dBc/Hz at 100 KHz and 1 MHz offset, respectively, for a low power consumption of 15 mW. The backgate QVCO demonstrates a wide frequency tuning range, a low phase noise, and a low power consumption. The corresponding figure-of-merit of the QVCO is -186 dBc/Hz. (C) 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2682-2685, 2010: View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25564

A low-voltage quadrature up-conversion CMOS mixer for 5-GHz wireless communication applications is designed with a TSMC 0.18-mum process. The fold-switching technique is used to implement the low-voltage double balanced quadrature mixer. A miniature lumped-element microwave broadband rat-race hybrid and RLC shift network are used for the local oscillator and the intermediate frequency port design, respectively. The measured results demonstrate that the mixer can reach a high conversion gain, a low noise figure (NF), and a high linearity. The mixer exhibits improvement in noise, conversion gain, and image rejection. The mixer shows a conversion gain of 16 dB, a noise figure of 12.8 dB, an image rejection of 45 dB, while dissipating 15.5 mW for an operating voltage at 1 V.

This paper presents the design of a novel wide output current range dual-mode dc to dc step-down (Buck) switching regulator/converter. The converter can adaptively switch between pulsewidth modulation (PWM) and pulse-frequency modulation (PFM) both with very high conversion efficiency. Under light load condition the converter enters PFM mode. The function of closing internal idle circuits is implemented to save unnecessary switching losses. The converter can be switched to PWM mode when the load current is greater than 100 mA. Soft start operation is designed to eliminate the excess large current at the start up of the regulator. The chip has been fabricated with a TSMC 2P4M 0.35 mu m polycide CMOS process. The range of the operation voltage is from 2.7 to 5 V, which is suitable for single-cell lithium-ion battery supply applications. The maximum conversion efficiency is 95 % at 50 mA load current. Above 85 % conversion efficiency can be reached for load current from 3 to 460 mA.

This paper presents the design of a low-cost programmable controller integrated circuit (IC) for general power electronics applications. The architecture of the programmable controller IC consists of 10-bit ADC and DAC, programmable counter array (PCA), which is configured to function as PWM, and a control unit (processor) for regulation. The processor unit is configured as digital compensator, through fewer program steps to perform accurate compensation on the voltage control loop of the converter system. Limit-cycle oscillation is minimized through inclusion of a sufficiently low integral gain term in the control law. A hybrid control method is first used to control the input voltage and current waveforms to achieve a unity power factor correction. It is observed that the programmable converter achieves the high efficiency power conversion. The conversion efficiency of the digital controlled boost converter is 91% with a 0.8% ripple voltage performance. While in power factor correction (PFC) circuit application, the power factor and output ripple voltage of converter are 0.995 and 0.93%, respectively. The chip is implemented with TSMC 0.25 um CMOS process.

The design of a new high-efficiency switching power amplifier with an ultralow-power spread spectrum clock generator (SSCG) is first reported in this paper. An effective low-power frequency modulation method is first proposed to reduce the electromagnetic interference of the pulse width modulation class D power amplifier without degrading its power efficiency. Also, a simple RC voltage feedback circuit is used to reduce the total harmonic distortion (THD). This amplifier proves to be a cost-effective solution for designing high fidelity and high efficiency audio power amplifiers for portable applications. Measurement results show that the power efficiency and THD can reach 90% and 0.05%, respectively. The power dissipation of the SSCG is only 112 mu W. The harmonic peaks of the switching frequency are greatly reduced when the SSCG technique is applied to the amplifier design. The impact of the SSCG on the THD of the class D power amplifier is also first reported in this paper. This switching power amplifier is implemented using a Taiwan Semiconductor Manufacture Company (TSMC) 0.35-mu m CMOS process.

This paper presents a new predistortion linearization scheme for single-sideband mixers to be used for removing unwanted harmonics and intermodulation products of the digital IF in an heterodyne transmitter. The proposed algorithm, called poly-harmonic predistortion linearization, relies on an orthogonal expansion in the frequency domain of the nonlinearities for the mixer modeling. It takes into account memory effects that are piece-wise quasi-memoryless and enables the independent cancellation of unwanted spurious sidebands of the digital IF harmonics. The poly-harmonic predistortion linearization scheme for the weak-nonlinear regime was implemented in a field-programmable gate array and experimentally investigated for the linearization of a four-path polyphase single-sideband upconverter. The ability of the poly-harmonic predistortion algorithm to linearize the four-path polyphase mixer for input signals with high envelope fluctuation is demonstrated. 70-dBc 62-dBc 60-dBc spurious rejection and 18-dB/10-dB/8-dB linearization improvement of the third-order distortions are achieved for a two-tone RF signal, a 64-tone 10-MHz bandwidth multisine signal and orthogonal frequency-division multiplexing signal, respectively. The combination of the polyphase multipath technique and the poly-harmonic predistortion linearization technique offers an attractive filterless approach for the development of multimode broadband software-defined radio.

An asynchronous architecture dual-mode DC-DC buck converter utilizing an external Schottky diode was evaluated and implemented in SMIC 0.13 mu m 1P6M 3.3/2.5V Logic Signal CMOS technology. This paper aimed to employ a simple, low cost, and small solution size with on-chip compensation implementation while not compromising high efficiency requirement. Maintaining high efficiency is achieved by adopting a switch-mode pulse-width modulation (PWM) and pulse-frequency modulation (PFM) control schemes for heavy load and light load, respectively. Other features for this design include a proposed simple internal circuit structure for over-temperature (OTP) and over-voltage protection (OVP), and a soft-start operation to suppress the power-on inrush current and when OTP and OVP cease. This converter can operate at internally fixed 1.5 MHz with input voltage from 2.0 V to 3.6 V suitable for two thy batteries powered applications. A low output voltage is easily supported with 0.5 V feedback voltage reference. An overall peak efficiency was observed atabout 93.9 % and 84 % at Vout of 1.8 V and 1.2 V, respectively(1).

This paper presents an ultra-wideband (UWB) 3.1 similar to 8.2-GHz low- noise amplifier design. Rresistive shunt-feedback method is used to provide wideband input matching and low noise figure (NF). The cascade configuration is employed with the inductive source degeneration and an input three-section band-pass Chebyshev filter. The LNA operates at 1.5 Volt and consumes 16.2mW. At 3.1 similar to 8.2-GHz, this LNA has NF of 3.6dB, with(-)input return loss of -12.155 dB, output return loss of -12.75 dB, and power gain of 11.43dB. The circuit is designed with TSMC 0.18um single-poly-six-metal CMOS process.

This paper presents the design of a novel wide output current range dual-mode DC to DC step-down (Buck) switching regulator/converter. The converter can adaptively switch between pulse-width modulation (PWM) and pulse-frequency modulation (PFM) both with very high conversion efficiency. Soft start operation is designed to eliminate the excess large current at the start up of the regulator. The chip has been fabricated with a TSMC 2P4M 0.35 ? m polycide CMOS process. The range of the operation voltage is from 2.7 V to 5 V； which is suitable for single-cell lithium-ion battery supply applications. The maximum conversion efficiency is 95%at 50 mA load current. Above 85%conversion efficiency can be reached for load current from 3 to 460 mA.