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Now showing items 1 - 2 of 2

  • A LOW-PHASE-NOISE CMOS QUADRATURE VCO WITH PMOS BACK-GATE COUPLING

    Yeh, Mel-Ling   Lin, Yao-Chian   Liou, Wan-Rone   Kuo, Sheng-Hing   Roblin, Patrick   Chang, Chung Cheng  

    A new PMOS backgate quadrature voltage controlled oscillator (QVCO) is designed and implemented using TSMC 0.18 mu m 1P6M CMOS technology. The phase noise of the PMOS hack-gate coupled QVCO operating at 1.5 V is measured to be -100 dBc/Hz and -125.08 dBc/Hz at 100 KHz and 1 MHz offset, respectively, for a low power consumption of 15 mW. The backgate QVCO demonstrates a wide frequency tuning range, a low phase noise, and a low power consumption. The corresponding figure-of-merit of the QVCO is -186 dBc/Hz. (C) 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2682-2685, 2010: View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25564
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  • A low-voltage 5-GHz quadrature up-conversion mixer for wireless transmitter

    Yeh, Mei-Ling   Kuo, Sheng-Hing   Liou, Wan-Rone  

    In this paper, a low-voltage CMOS quadrature up-conversion mixer for 5-GHz wireless communication applications is designed. The simulation results demonstrate the mixer can reach a high conversion gain (CG), a low noise figure (NF), and a high linearity (IIP3). A miniature lumped-element microwave broadband rat-race hybrid and RLC shift network are used for the LO and the IF port design, respectively. The mixer exhibits a 3dB improvement in noise and conversion gain, and the image rejection is -35dBc. The mixer achieves noise. figure of 12.8 dB, a conversion gain of 15 dB, an output third intercept point at 0dBm, while dissipating 15mW for operating voltage at I V. The mixer is designed with TSMC 0.18 um process.
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