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Now showing items 1 - 16 of 47

  • National Centre on Artificial Intelligence: India on the Move

    Kumar, Mamidala Jagadesh  

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  • Nanotube Junctionless FET: Proposal, Design, and Investigation

    Sahay, Shubham   Kumar, Mamidala Jagadesh  

    In this paper, we propose a nanotube (NT) JLFET for significantly improved performance in the sub-10-nm regime. We show that the tunneling width at the channel-drain interface and the source-to-channel barrier height are considerably increased in the NT JLFET due to the presence of the core gate. Therefore, the lateral band-to-band-tunneling-induced parasitic bipolar junction transistor action is diminished in the off-state of NT JLFET, leading to a significantly high on-state to off-state current ratio of similar to 10(7) even for a channel length of 7 nm. Furthermore, we demonstrate that the spacer length and dielectric constant and the core gate diameter can be used as design parameters to further improve the performance of the NT JLFETs. Therefore, we also provide the necessary design guidelines for NT JLFETs.
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  • Realizing Efficient Volume Depletion in SOI Junctionless FETs

    Sahay, Shubham   Kumar, Mamidala Jagadesh  

    In this paper, we provide a simple and effective solution to realize efficient volume depletion and therefore, significantly reduce the OFF-state leakage current of a junctionless FET (JLFET) by replacing the SiO2 by HfO2 in the buried oxide (BOX). Using calibrated 2-D simulations, we show that the JLFET with a high-k BOX (HB JLFET) exhibits a considerably high I-ON/I-OFF ratio of similar to 10(6) even for a channel length of 20 nm. Further, we demonstrate that the use of a high-k BOX leads to a reduction in both gate capacitance C-g and gate-to-drain feedback (Miller) capacitance C-gd.
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  • Insight into Lateral Band-to-Band-Tunneling in Nanowire Junctionless FETs

    Sahay, Shubham   Kumar, Mamidala Jagadesh  

    In this paper, we investigate the nature of lateral band-to-band-tunneling (L-BTBT) component of gate-induced drain leakage (GIDL) in different nanowire junctionless FET (NWJLFET) configurations for the first time. Although the NW junctionless accumulation mode (JAM) FET has a larger ON-state current compared with the NWJLFETs, we demonstrate that the L-BTBT GIDL is larger in the NWJAMFET compared with the NWJLFET. Furthermore, we explore for the first time the application of a dual-material gate (DMG) in the NWJAMFET to suppress the L-BTBT GIDL. Using calibrated 3-D simulations, we show that the OFF-state current in the DMG NWJAMFET is reduced significantly by six orders of magnitude leading to a considerable ON-state to OFF-state current ratio (I/I-OFF) of similar to 10(10). Furthermore, the DMG NWJAMFET offers: 1) an enhanced ON-state current and 2) a significantly reduced OFF-state current compared with the NWJLFETs. Furthermore, we also demonstrate that the DMG NWJAMFET exhibits a higher transconductance than the single material gate NWJAMFET in the saturation region. In addition, we also show that there is a tradeoff between the off-state current and the intrinsic delay and the cut-off frequency in the DMG NWJAMFET. Therefore, we provide the design guidelines for appropriately choosing the work functions of the dual gates and the ratio of the length of the dual gates to the total gate length.
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  • What is in store in January-February 2019 issue of IETE Technical Review?

    Kumar, Mamidala Jagadesh  

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  • Schottky Biristor: A Metal-Semiconductor-Metal Bistable Resistor

    Kumar, Mamidala Jagadesh   Maram, Maheedhar   Varma, P. Pradeep  

    In this brief, we report a novel metal-semiconductor-metal-based bistable resistor, called the Schottky biristor, whose performance is superior to the existing bipolar junction transistor-based biristors. The proposed device can be realized by joining symmetrical Schottky contacts back to back. Apart from being free of the thermal budgets involved in the fabrication of p-n junctions in a biristor, the Schottky biristor also has much lower latch voltages (latch-up voltage of 1.62 V and latch-down voltage of 1.18 V) and a reasonable latch window (0.44 V) as demonstrated by our simulation results.
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  • Schottky Biristor: A Metal-Semiconductor–Metal Bistable Resistor

    Kumar, Mamidala Jagadesh   Maram, Maheedhar   Varma, P. Pradeep  

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  • 1-T Capacitorless DRAM Using Bandgap-Engineered Silicon-Germanium Bipolar I-MOS

    Lahgere, Avinash   Kumar, Mamidala Jagadesh  

    In this paper, a 1-Transitor (1-T) capacitorless dynamic random access memory (DRAM) using bandgap-engineered silicon-germanium Bipolar ionization metal oxide semiconductor field effect transistor (I-MOS) is investigated through numerical simulations. We have demonstrated the application of the proposed Si0.6Ge0.4 Bipolar I-MOS for realization of a 1-T capacitorless DRAM. The proposed device can achieve hysteresis at significantly lower drain voltages (V-LD =3D 0.45 V to V-LU =3D1.15 V), in comparison to the inversion mode device (V-LD =3D 8 V to V-LU =3D 11 V). In addition, the proposed 1-T capacitorless DRAM exhibits a wider hysteresis window (Delta V) of the order similar to 700 mV and a sensing margin (M) of similar to 5 orders in comparison to the inversion mode based 1-T capacitorless DRAM. Moreover, the proposed 1-T capacitorless DRAM exhibits the retention time of similar to 750 msec and similar to 320 msec for T =3D 25 degrees C and T =3D 85 degrees C, respectively. The proposed 1-T capacitorless DRAM also shows nondestructive read and an extreme long-term endurance. Therefore, the results presented in this paper can provide an opportunity for future DRAM design in deep nanometer technology.
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  • Junctionless Impact Ionization MOS: Proposal and Investigation

    Ramaswamy, Sindhu   Kumar, Mamidala Jagadesh  

    We propose a novel junctionless impact ionization MOS (JIMOS) on a p-type silicon film using charge plasma concept. This device does not have metallurgical junctions and requires no impurity doping for creating the source and drain. This makes the JIMOS combine the benefits of an impact ionization MOS (IMOS) (steep subthreshold slope) and a junctionless field-effect transistor (JLFET) (low thermal budget process). Using 2-D simulations, we show that the performance of the JIMOS is analogous to that of a corresponding IMOS in which the source and drain regions are created by impurity doping. The proposed idea can pave the way for fabricating the IMOS using a low thermal budget process similar to that of a JLFET.
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  • What is in store in the May-June 2019 issue of IETE Technical Review?

    Kumar, Mamidala Jagadesh  

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  • GaAs Tunnel Diode With Electrostatically Doped n-Region:Proposal and Analysis

    Kumar, Mamidala Jagadesh   Sharma, Shailesh  

    In n-type GaAs, the electron concentration saturates to a value close to 10(19)/cm(3) even when the chemically doped impurity concentration is more than the value. Therefore, the peak current density in GaAs-based tunnel diodes is limited by the difficulty in realizing the n-type GaAs using dopant diffusion. In this brief, we demonstrate that the n-type region can be electrostatically induced in p-type GaAs using a metal electrode of appropriate work function. This obviates the need for n-type chemical impurity doping in GaAs. Using calibrated 2-D simulations, we demonstrate that the proposed GaAs tunnel diode with electrostatically doped n-region on p-type GaAs not only exhibits significantly improved peak current but also is easy to fabricate.
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  • GaAs Tunnel Diode With Electrostatically Doped n-Region: Proposal and Analysis

    Kumar, Mamidala Jagadesh   Sharma, Shailesh  

    In n-type GaAs, the electron concentration saturates to a value close to 1019 /cm3 even when the chemically doped impurity concentration is more than the value. Therefore, the peak current density in GaAs-based tunnel diodes is limited by the difficulty in realizing the n-type GaAs using dopant diffusion. In this brief, we demonstrate that the n-type region can be electrostatically induced in p-type GaAs using a metal electrode of appropriate work function. This obviates the need for n-type chemical impurity doping in GaAs. Using calibrated 2-D simulations, we demonstrate that the proposed GaAs tunnel diode with electrostatically doped n-region on p-type GaAs not only exhibits significantly improved peak current but also is easy to fabricate.
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  • What is in Store in the May-June 2017 issue of IETE Technical Review?

    Kumar, Mamidala Jagadesh  

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  • What is in store in the January-February 2020 issue of IETE Technical Review?

    Kumar, Mamidala Jagadesh  

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  • A Tunnel Dielectric-Based Junctionless Transistor With Reduced Parasitic BJT Action

    Lahgere, Avinash   Kumar, Mamidala Jagadesh  

    In this paper, we demonstrate a tunnel dielectric-based junctionless transistor, referred as TD JLT, which consists of a thin dielectric layer in the middle of the channel region of a JLT leading to a drastically reduced parasitic bipolar junction transistor (BJT) action. Using calibrated 2-D simulations, we show that the proposed TD JLT has a significantly low off-state leakage current due to the presence of a tunneling barrier, and an enhanced sourceto- channel barrier height, which results in a diminished parasitic BJT action in the off-state. Further, the proposed TD JLT exhibits an extremely high I-ON/I-OFF ratio of similar to 1.1x10(7) for a channel length of 20 nm and a significant(I-ON/I-OFF) ratio of similar to 10(2) even for a channel length of 10 nm.
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  • Junctionless Biristor: A Bistable Resistor Without Chemically Doped P-N Junctions

    Kumar, Mamidala Jagadesh   Maheedhar, Maram   Varma, P. Pradeep  

    In this paper, using 2-D simulations, we report a novel junction-less biristor in which the emitter and collector regions are created by applying the charge plasma concept on a P-doped silicon film. Since no chemical doping is required, the junction-less biristor can be realized with a low thermal budget. We demonstrate that the junction-less biristor exhibits not only a significant low latch-up voltage (2.0 V) but also has a large latch window (0.66 V) when compared to that of a conventional silicon biristor with similar parameters. The reasons for this improved performance are discussed.
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