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Now showing items 1 - 4 of 4

  • An 11-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation

    Gu, Weiru   Ye, Fan   Ren, Junyan  

    This paper presents an 11-bit 22-MS/s 0.6-mW successive approximation register (SAR) analog-to-digital converter (ADC) using SMIC 65-nm low leakage (LL) CMOS technology with a 1.2 V supply voltage. To reduce the total capacitance and core area the split capacitor architecture is adopted. But in high resolution ADCs the parasitic capacitance in the LSB-side would decrease the linearity of the ADC and it is hard to calibrate. This paper proposes a parasitic capacitance compensation technique to cancel the effect with no calibration circuits. Moreover, dynamic circuits are used to minimize the switching power of the digital logic and also can reduce the latency time. The prototype chip realized an 11-bit SAR ADC fabricated in SMIC 65-nm CMOS technology with a core area of 300 times 200 mum 2. It shows a sampling rate of 22 MS/s and low power dissipation of 0.6 mW at a 1.2 V supply voltage. At low input frequency the signal-to-noise-and-distortion ratio (SNDR) is 59.3 dB and the spurious-free dynamic range is 72.2 dB. The peak figure-of-merit is 36.4 fJ/conversion-step.
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  • A single-ended 10-bit 200 kS/s 607\r μ\r W SAR ADC with an auto-zeroing offset cancellation technique

    Gu, Weiru   Wu, Yimin   Ye, Fan   Ren, Junyan  

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  • Switch-back based on charge equalization switching technique for SAR ADC

    Gu, Weiru   Ye, Fan   Ren, Junyan  

    A switch-back based on charge equalization switching technique for successive-approximation-register (SAR) analog-to-digital converters (ADCs) is proposed. With the proposed switching technique the average switching energy is reduced by 96.86% as compared with the conventional method. This switching scheme can also reduce the total capacitance about 75% with the comparison of the conventional architecture. With the proposed switching scheme the common mode voltage shifts only by 1LSB during all conversion steps, so the dynamic offset of comparator becomes negligible in this case.
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  • A single-ended 10-bit 200 kS/s 607 mu W SAR ADC with an auto-zeroing offset cancellation technique

    Gu, Weiru   Wu, Yimin   Ye, Fan   Ren, Junyan  

    This paper presents a single-ended 8-channel 10-bit 200 kS/s 607 mu W synchronous successive approximation register (SAR) analog-to-digital converter (ADC) using HLMC 55 nm low leakage (LL) CMOS technology with a 3.3 V/1.2 V supply voltage. In conventional binary-encoded SAR ADCs the total capacitance grows exponentially with resolution. In this paper a CR hybrid DAC is adopted to reduce both capacitance and core area. The capacitor array resolves 4 bits and the other 6 bits are resolved by the resistor array. The 10-bit data is acquired by thermometer encoding to reduce the probability of DNL errors which are typically present in binary weighted architectures. This paper uses an auto-zeroing offset cancellation technique that can reduce the offset to 0.286 mV. The prototype chip realized the 10-bit SAR ADC fabricated in HLMC 55 nm CMOS technology with a core area of 167 x 87 mu m(2). It shows a sampling rate of 200 kS/s and low power dissipation of 607 mu W operates at a 3.3 V analog supply voltage and a 1.2 V digital supply voltage. At the input frequency of 10 kHz the signal-to-noise-anddistortion ratio (SNDR) is 60.1 dB and the spurious-free dynamic range (SFDR) is 68.1 dB. The measured DNL is C 0:37/0: 06 LSB and INL is C 0: 58/0:22 LSB.
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