In this paper, we study the effects of non-uniform channel doping on junctionless transistor (JLT) using 3D quantum simulations. The JLT devices require a uniformly doped ultrathin channel. Although we take uniform doping for study, in practice, it will be technologically difficult to obtain. For technological reason, after thermal annealing, the impurity profile in semiconductor device becomes uniform along lateral channel direction and non-uniform along vertical direction. Here, we show that this directly affects the short channel behaviour and reduces on-current.

This paper proposes a laterally graded junctionless transistor taking peak doping concentration near the source and drain region, and a gradual decrease in doping concentration towards the center of the channel to improve the IOFF and ION/ IOFF ratio. The decrease of doping concentration in the lateral direction of the channel region depletes a greater number of charge carriers compared to the uniformly doped channel in the OFF-state, which in turn suppresses the OFF state current flowing through the device without greatly affecting the ON state current.

This paper proposes a junctionless tunnel field effect transistor (JLTFET) with dual material gate (DMG) structure and the performance was studied on the basis of energy band profile modulation. The two-dimensional simulation was carried out to show the effect of conduction band minima on the abruptness of transition between the ON and OFF states, which results in low subthreshold slope (SS). Appropriate selection of work function for source and drain side gate metal of a double metal gate JLTFET can also significantly reduce the subthreshold slope (SS), OFF state leakage and hence gives improved I (ON)/I (OFF).

In this paper we examined the short channel behavior of junction less tunnel field effect transistor (JLTFET) and a comparison was made with the conventional MOSFET on the basis of variability of device parameter. The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. The JLTFET exhibits an improved subthreshold slope (SS) of 24 mV/decade and drain-induced barrier lowering (DIBL) of 38 mV/V as compared to SS of 73 mV/decade and DIBL of 98 mV/V for the conventional MOSFET. The simulation result shows that the impact of length scaling on threshold voltage for JLTFET is very less as compared to MOSFET. Even a JLTFET with gate length of 10 nm has better SS than MOSFET with gate length of 25 nm, which enlightens the superior electrostatic integrity and better scalability of JLTFET over MOSFET.

we demonstrate the design of a triple gate n-channel junctionless transistor that we call a junctionless tunnel field effect transistor (JLTFET). The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. Simulation shows significant improvement compared to simple junctionless field effect transistor both in I (ON)/I (OFF) ratio and subthreshold slope. Here, junctionless tunnel field effect transistors with high-k dielectric and low-k spacers are demonstrated through simulation and shows an ON-current of 0.25 mA/mu m for the gate voltage of 2 V and an OFF current of 3 pA/mu m (neglecting gate leakage). In addition, our device shows optimized performance with high I (ON)/I (OFF) (similar to 10(9)). Moreover, a subthreshold slope of 47 mV/decade is obtained for a 50 nm gate length of simulated JLTFET at room temperature which indicates that JLTFET is a promising candidate for switching performance.