In this paper, we explain the problem of dramatic OFF-state leakage in junctionless tunnel field effect transistor (JLTFET) for a channel thickness greater than 10 nm. In JLTFET, with channel width greater than 10 nm, the depletion region primarily remains confined below the dielectric-semiconductor interface. Hence, we tend to incur significant leakage through the center of the device. With the help of 2D device simulations, we demonstrate that the cause of the leakage current is predominantly due to thermal injection in the source region and is concentrated through the center of the device. We suggest a technique of using a lightly doped source region, below the p-gate to increase the barrier and prevent any leakage. The proposed alteration records an improved I (ON)/I (OFF) ratio for JLTFET for a channel of width 20 nm.

We present a GaSb/InAs junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the present device architecture, which can be exploited as a digital switching device for sub 20 nm technology. Numerical simulations resulted in an I-OFF of similar to 8 x 10(-17) A/mu m, I-ON of similar to 9 mu A/mu m, I-ON/I-OFF of similar to 1 x 10(11), subthreshold slope of 9.33 mV/dec and DIBL of similar to 87 mV/V for GaSb/InAs JLTFET at a temperature of 300 K, gate length of 20 nm, HfO2 gate dielectric thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and V-DD of 0.4 V.

Tunnel field-effect transistor (TFET) devices are gaining attention because of good scalability and they have very low leakage current. However, they suffer from low ON-current and high threshold voltage. In this paper, we present III-V heterojunctionless TFET (H-JLTFET) for circuit applications. This paper elaborates on interfacing of III-V with group IV semiconductors for heterojunction. Implementing heterojunction and bandgap engineering, we found that devices have significantly improved performance with very high speed even at very low operating voltage. As there is no doping junction present, future scaling could be feasible along with much higher speed of charge carriers than in silicon. GaAs:Si, Si:Si0.3Ge0.7, Si:InAs, and GaAs:Ge, H-JLTFET interface for 20-nm gate length (EOT = 2 nm) and dielectric, HfO2 at V-GS = 1 V and temperature of 300 K have I-ON of 0.02-12.5 mA/mu m, I-ON/I-OFF of 10(5) - 10(12), and subthreshold swing (average) of 16-74 mV/decade.

In this paper we have proposed an optimal design for a hetero- junctionless tunnel field effect transistor (TFET) using HfO2 as a gate dielectric. The device principle and performance are investigated using a 2D simulator. During this work, we investigated the transfer characteristics, output characteristics, transconductance, Gm, output conductance, GD, and C-V characteristics of our proposed device. Numerical simulations resulted in outstanding performance of the H-JLTFET resulting in I-ON of similar to 0.23 mA mu m(-1), I-OFF of similar to 2.2 x 10(-17) A mu m-(1,) I-ON/I-OFF of similar to 10(13), sub-threshold slope (SS) of similar to 12 mV dec(-1) , DIBL of similar to 93 mV V-1 and V-th of similar or equal to 0.11 V at room temperature and VDD of 0.7 V. This indicates that the H-JLTFET can play an important role in the further development of low power switching applications.

In this paper, the characteristics of a novel device structure, uniformly doped ultra-deep-submicron poly-Si barrier modulated thin film transistor (BM-TFT), are investigated and compared with conventional poly-Si TFT. Use of uniform doping provides a solution from problems associated with random dopant fluctuations. The suppression of the leakage current of the TFT by introducing barrier modulation is verified and presented. The device is optimized with respect to channel length, doping of channel, spacer dielectric and gate dielectric material. Simulations resulted in I-OFF of -2 x 10(-11) A mu m(-1), I-ON of -2mA mu m(-1), I-ON/I-OFF of 10(8), subthreshold slope of 144 mV/dec and DIBL of 119 mV V-1 for PolyGate/HfO2/Poly-Si coplanar BM-TFT at temperature. of 300 K, gate length of 60 nm, oxide thickness of 5 nm, film thickness of 10 nm, low-k spacer thickness of 20 nm and V-DD of 2.5 V.