A novel high precision high order curvature-compensated bandgap reference (BGR) is presented in this paper designed using the subthreshold current of self-cascode transistors in standard digital 0.18 mu m CMOS process. Simultaneously its temperature coefficient is typically 4.6 ppm/degrees C in the temperature range of -25 to 120 degrees C with a supply current of 17.25 mu A. A power supply rejection ratio (PSRR) of -51 dB is achieved while the layout area is no more than 0.0022 mm(2).
An equivalent-circuit model of shield differential through-silicon vias (SDTSVs) in 3-D integrated circuits (3-D ICs) is proposed in this paper. The proposed model is verified using the 3-D full-wave field solver High Frequency Simulator Structure, showing that it is highly accurate up to 100 GHz. Furthermore, a full-wave extraction method for the resistance-inductance-capacitance-conductance (RLCG) parameters of SDTSVs is also proposed in this paper, which can be applied to all of differential transmission lines. It is shown that the results of the RLCG parameters obtained from the full-wave extraction method agree well with that from the analytical calculation up to 100 GHz, further validating the accuracy of the proposed model. Finally, using the proposed model, a deep analysis of electrical characteristics of SDTSVs is carried out to provide helpful design guidelines for them in future 3-D ICs.
A resolution configurable ultra-low power SAR ADC in 0.18 mu m CMOS process is presented. The proposed ADC has maximum sampling rate of 100 KS/s with configurable resolution from 8 to 10 b and operates at a supply of 0.6 V. Two-stage bootstrapped switch and voltage boosting techniques are introduced to improve the performance of the ADC at low voltage. To reduce the power consumption of the analog components of the ADC, monotonic capacitor switching procedure and fully dynamic comparator are utilized. The implementation of dynamic logic further reduces the power of the digital circuits. Post-layout simulation results show that the proposed SAR ADC consumes 521 nW and achieves an SNDR of 60.54 dB at 10 b mode, resulting in an ultra-low figure-of-merit of 6.0 fJ/conversion-step. The ADC core occupies an active area of only 350 x 280 mu m(2).
An automatic mode low-jitter pulsewidth control loop (PWCL) with enhanced operation frequency is presented in this paper. Using the automatic mode selector (AMS), the proposed PWCL can operate between pulsewidth modulating mode and tracking mode adaptively, avoiding extra power dissipation when a 50% duty cycle input clock is added. Based on the analysis of the delay time between the fixed falling edge and the rising edge generated by PWCL cycle, an auto delay time adjusting delay stage (ADTDS) is proposed to expand the locking frequency range of PWCL. Moreover, an improved charge pump and a novel delay stage are utilized to decrease the supply-induced jitter. The experimental results demonstrate that the proposed PWCL can lock the clock duty cycles for no more than 50 +/- 1% with 10-90% input duty cycle from 5 MHz to 750 MHz. At pulsewidth modulating mode, the measurement power dissipation and peak-to-peak jitter are 9.52 mW and 7.72 ps (rising edge) and 9.45 ps (falling edge), respectively, while at tracking mode, 0.6 mW and 10.1 ps achieved with an operating frequency of 750 MHz. The core area of chip is 220 mu mx310 mu m(2).
A fast-locking, high-precision and low-jitter pulsewidth control loop for high-speed pipelined ADC is presented. Only through controlling the delay of rising edge to adjust duty cycle, the clock jitter could be suppressed greatly. An improved charge pump with a follower circuit and self-biased loop was designed to decrease the voltage ripples for higher accuracy and lower jitter. A start-up circuit was adopted to enable the pulsewidth control loop (PWCL) lock rapidly. Using SMIC 0.18 mu m 3.3V CMOS Spice process model, the simulation results show that within 180 ns the PWCL can lock the clock duty cycles for the accuracy of 50 +/- 1% with 10%similar to 90% input duty cycle from 50 MHz to 250 MHz. The rms-jitter is 73 fs at 250 MHz.
Based on the impact of the scattering effect on latency and bandwidth, this letter presents the quality-factor model that optimizes latency and bandwidth effectively with consideration of the scattering effect. Then, we get the optimization analytical model with target interconnect linewidth and line spacing by the curve-fitting method. The proposed model has been verified and compared for nanoscale CMOS technology. The optimization model is simple, and we can apply it to the interconnect system optimal design of nano-CMOS integrated circuits.
Primary-side controlled universal-line flyback converters have been widely used in low-power applications due to their simplicity, low standby power, and low cost. However, conventional OCP schemes normally cause too large a variation in output current when the input voltage varies. This paper proposes a selfcompensating OCP circuit to achieve a high-precision constant current at different input voltages which can be used in flyback converters working in discontinues conduction mode. It consists of a CS S/H circuit and a dynamic OCP voltage reference circuit. Compared with conventional OCP circuits, it does not need an extra compensation circuit. To verify the feasibility and performance of the proposed circuit, an IC controller that uses the proposed OCP circuit has been designed and fabricated in 0.35 mu m 5-V/40V high-voltage CMOS technology. Experimental results show that the constant output current precision of the prototype is within +/- 1% when the input line voltage changes from 85 to 265 Vac. In the common line voltage range (110-220 Vac), the output current regulation accuracy can reach a level as high as +/- 0.3%.
In this letter, the Resistance Inductance Capacitance Conductance (RLCG) parameters of carbon nanotube through silicon via (CNT-TSV) are modeled and a transmission line (TL) model is established through ABCD matrix. The impact of their geometrical and material parameters on the TSV transmission characteristics is analyzed over a wideband of frequency using the proposed model. An optimization methodology using air gap insulator is proposed to improve the transmission performance. SPICE results show that a 30.83% reduction in insertion loss and a 40.72% increase in eye open area, respectively.
Negative capacitance FET (NCFET) has become a research topic of interest in recent years due to its interesting properties. It has the ability to retain the polarization state even in the absence of electric field. By virtue of this ability, it can be designed as a nonvolatile memory. NCFET can also be configured as a steep-slope switch and thereby providing energy efficiency while used in digital designs. However, the benefits offered by NCFETs for analog circuit domain has not well reported. In this paper, we analyze the impact of body effect on an NCFET-based bootstrapped switch and illustrate that the linearity of NCFET-based switch can be improved resulting from the internal amplification of the employed NCFET. When designed at 0.6-V supply (V-dd), results show that the variation of the on resistance of the bootstrapped switch is about 67 Omega during the sampling period, which is one-third smaller than the MOSFET-based switch. As a result, the sampling linearity is improved and the distortion at the output can be decreased. On condition that the Nyquist input frequency is 10 MHz, the proposed NCFET-based bootstrapped switch succeeds in improving the total harmonic distortion performance by 16.7 dB, compared with that of a conventional MOSFET based bootstrapped switch.
This brief presents a 40-nW 0.5-V supply voltage and 0.24-V output reference for an energy harvester. The emitter-base voltage of a PNP transistor is divided by the presented switch capacitor circuit to obtain the low output reference. The resistorless proportional-to-absolute-temperature circuit and the low-voltage high-power-supply-rejection-ratio current source are used to improve the accuracy and line regulation performance of the reference. The proposed bandgap reference is implemented in a 0.18-mu m standard complementary metal-oxide-semiconductor process and has a total area of 0.058 mm(2). Test results show that the minimum supply voltage is 0.5 V due to the clock bootstrap and 2 x VDD doubler. The line regulation is about 1.1 mV/V in the supply voltage range of 0.5-0.9 V. With 3-bit trimming, the temperature coefficient of 58 ppm/degrees C in the range of -25 degrees C-85 degrees C and the accuracy of 0.9% (3 delta) can be achieved.
The concept of a distortionless through silicon via (TSV), which uses a multiwalled carbon nanotube (MWCNT) as conductor material, is proposed. The design requirements and the design method for the distortionless TSV are presented. In the high-frequency band, the propagation constant of the traditional Cu-TSV will deviate from the linear function of the frequency because of the skin effect, inducing the transmission signal distortion. MWCNT bundles have properties where the resistance and the inductance are almost constant with the frequency, which can meet the design requirements for a distortionless TSV. Compared with the identical dimensions Cu-TSV, the TSV designed by using the proposed method with MWCNT bundles as the conductor material has the preferable linearity of the propagation constant with the frequency in the high-frequency band, so that it can reduce the distortion of the transmission signal.