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Now showing items 1 - 16 of 167

  • An encapsulated packet-selection routing for network on chip

    Liu, Lu   Ma, Rui   Zhu, Zhangming  

    Enhanced performance and reduced overhead are critical to Network-on-Chip (NoC) design. Locally congestion-aware (LCA) routing decisions have been proved as effective solutions. In this paper, we present an encapsulated packet-selection routing (EnPSR) that provides admissible output channels with available adjacent VCs at packet injection stage, which selects injected packets for available output channels; conventional routing computation units in EnPSR router can be eliminated. Evaluation results show that the proposed EnPSR yields a reduced average packet latency by 12.1% and an improved throughput by 3.6%, the area and power costs of EnPSR are reduced by 11.3% and 9.6% respectively.
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  • Broadband inductance modeling of TXVs for 3D interconnection

    Liu, Yang   Zhu, Zhangming   Liu, Xiaoxian   Guo, Lixin   Yang, Yintang  

    In this paper, a broadband closed-form expression for the parasitic inductance of Through-X Vias (TXVs) with a frequency up to 100 GHz is proposed. The rigorous formulas related to the geometrical parameters are derived considering the proximity effect and the skin effect. The proposed model can accurately reflect the change in inductance caused by magnetic flux variation at high frequency. The inductance model is verified by comparing with the 3-D full-wave electromagnetic solver High Frequency Simulator Structure (HFSS) in whole frequency range considered. The proposed model and HFSS results show accordance with each other over large radius range, with a maximum error of 4.6%.
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  • A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique

    Shen, Yi   Tang, Xiyuan   Shen, Linxiao   Zhao, Wenda   Xin, Xin   Liu, Shubin   Zhu, Zhangming   Sathe, Visvesh S.   Sun, Nan  

    This article presents a reference ripple cancellation technique for high-speed successive approximation register analog-to-digital converters (SAR ADCs) to address the reference voltage settling issue. Unlike prior techniques that aim to minimize the reference ripple, this article proposes a new perspective: it provides an extra path for the full-sized reference ripple to couple to the comparator but with an opposite polarity, so that the effect of the reference ripple is canceled out, thus ensuring an accurate conversion result. To verify the proposed technique, a prototype 10-bit 120-MS/s SAR ADC is fabricated in a 40-nm CMOS process. The proposed ripple cancellation technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL)/differential non-linearity (DNL) by ten times. Overall, the ADC achieves an SNDR of 55 dB with only 3-pF reference decoupling capacitor.
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  • A 10-Bit 5 MS/s VCO-SAR ADC in 0.18-mu m CMOS

    Xie, Yi   Liang, Yuhua   Liu, Maliang   Liu, Shubin   Zhu, Zhangming  

    This brief presents a 10-bit 5 MS/s hybrid analog-to-digital converter (ADC) combining successive approximation register (SAR) with voltage-controlled oscillator (VCO) in 0.18-mu m CMOS. Non-ideal factors from practical circuit implementations are theoretically considered and modeled in Simulink. To improve the linearity and the reliability of the bootstrapped switch circuit, the body-effect compensation is adopted. The asynchronous clock generation circuit with a variable-time control cell is presented, which optimizes the DAC settling time of the MSB DAC and LSB DAC in an SAR conversion. Verilog codes and a standard digital library make it possible to synthesize the most parts of the VCO-based Nyquist ADC, greatly reducing the design costs. At Nyquist input frequency and a 5 MS/s sampling rate, a signal-to-noise and distortion ratio of 56.7 dB and a spurious-free dynamic range of 72.2 dB are achieved, respectively. The core occupies 450 mu m x 280 mu m.
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  • A 6.3 GHz high bandwidth voltage-to-time converter with high linearity

    Duan, Jiangkun   Liu, Maliang   Zhu, Zhangming   Yang, Yintang  

    A voltage-to-time converter (VTC) architecture with high-bandwidth SFDR performance is presented. This VTC circuit is compatible with high-speed, high-bandwidth RF ADC systems. The proposed VTC utilizes the bottom plate sampling of the capacitor. A constant current source charges the capacitor and generates a ramp signal, which passes through the threshold comparator to output the time pulse signal. An independent sampling process RC loop is adopted to improve the input bandwidth of VTC. The circuit architecture of the cascode current source charging directly to the capacitor provides the linearity of the VTC. A novel bootstrapped switch is employed to further improve the linearity of VTC. The prototype VTC was fabricated in a 65 nm CMOS process with an active area of 0.008 mm(2). It exhibits an SNR of 62.7 dB and an SFDR of 54.6 dB for an input frequency of 6 GHz and a sampling rate of 500 MS/s under the TT process corner simulation.
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  • A 7b 400 MS/s pipelined SAR ADC in 65 nm CMOS

    Ding, Ruixue   Dang, Li   Lin, Hanchao   Sun, Depeng   Liu, Shubin   Zhu, Zhangming  

    This paper presents a 7-bit 400-MS/s pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with high reliability. To meet the high demand for medium resolution and high sampling speed, a modified switching scheme is adopted to resolve charge leakage problem and to improve the reliability of SAR ADC. Compared to the conventional architecture, the modified bootstrapped switch which uses two sampling MOSFETs is employed to increase the uniformity of sampling voltage and save the chip area. In addition, three parallel comparators are controlled by a novel asynchronous clock generator to minimize the latching error. The measurement result shows that the ADC, implemented in the 65-nm CMOS process, achieves the 40.83 dB signal-to-noise and distortion ratio (SNDR) and 64.75 dB spurious-free dynamic ranges (SFDR) at 400-MHz sampling frequency without additional digital calibration.
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  • Mismatch of Ferroelectric Film on Negative Capacitance FETs Performance

    Liang, Yuhua   Zhu, Zhangming   Li, Xueqing   Gupta, Sumeet Kumar   Datta, Suman   Narayanan, Vijaykrishnan  

    In this article, we analyze the impact of process variations of the ferroelectric film on the performance of the negative capacitance field-effect transistor (NCFET). Variations of the ferroelectric layer area (resulting from the variation of the transistor dimension sizes and the edge-effect), the ferroelectric layer thickness, the polarization, and the coercivity are taken into consideration to evaluate the impact on the NCFET performance. These results can serve as a guideline to improve both the circuit performance and yield for analog and digital circuits. To showcase this ability, the influence of these variations on the oscillating frequency of a five-stage ring oscillator and the mirroring current of a current mirror are analyzed. The results show that the distribution of the standard derivation of the oscillating frequency is 1.9 MHz on condition of T-FE =3D 14 nm, W-P/L-P =3D 1 mu m/45 nm, and W-N/L-N =3D 500/45 nm, and the standard derivation of the mirroring current is 0.17 mu A on condition of W =3D 1 mu m, L =3D 500 nm, and T-FE =3D 20 nm.
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  • Wideband Substrate Integrated Waveguide Bandpass Filter Based on 3-D ICs

    Liu, Xiaoxian   Zhu, Zhangming   Liu, Yang   Lu, Qijun   Yin, Xiangkun   Yang, Yintang  

    This paper proposes a substrate integrated waveguide bandpass filter (SIW BPF), exploiting the through-dielectric via (TDV)-based 3-D integrated circuit (3-D IC) technology. The SIW BPF is designed on the dielectric cavity that is etched on the traditional low-resistivity silicon (LRSi) in a 3-D IC system, acting as the insulating material between through-silicon via plugs and LRSi. This construction can reduce prominent eddy current losses in LRSi and coupling losses among TDV plugs for the millimeter-wave application. Benzocyclobutene and glass are chosen as the dielectric cavity due to the low dielectric constant and loss tangent. The detailed design procedure beginning from the normalized Chebyshev low-pass filter to the final optimized SIW BPF is presented. The filter having a 12.5% fractional bandwidth is centered at 159.67 GHz. The return losses and insertion loss across the passband are about -10 and -1.5 dB, respectively. Numerical analysis of the advanced design system and full-wave simulation results of Ansoft's HFSS show a good agreement.
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  • Repeater Insertion for Multi-Walled Carbon Nanotube Interconnects

    Liu, Peng-Wei   Cheng, Zi-Han   Zhao, Wen-Sheng   Lu, Qijun   Zhu, Zhangming   Wang, Gaofeng  

    Closed-form expressions for the optimized number and size of repeaters in multi-walled carbon nanotube (MWCNT) interconnects are presented. The contact resistance and inductive effects are taken into account. It is found that the propagation delay of MWCNT interconnects can be reduced effectively by inserting repeaters. However, the contact resistance has a significant influence on the optimized number and size of repeaters. Moreover, it is found that both the optimal number of repeaters and the minimum propagation delay are kept almost unchanged with the variation of carbon nanotube (CNT) kinetic inductance. The optimal number of repeaters in the MWCNT interconnect is much smaller than that in its Cu counterpart, thus saving chip area and power consumption.
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  • A 10-bit 100-MS/s 5.23-mW SAR ADC in 0.18-mu m CMOS

    Ma, Rui   Wang, Lisha   Li, Dengquan   Ding, Ruixue   Zhu, Zhangming  

    A 10-bit 100 MS/s energy-efficient successive-approximation analog-to-digital converter (SAR ADC) is presented in this paper. In order to improve the conversion rate and reduce power consumption as well, a modified spilt-capacitor V-cm-based switching scheme is proposed. By utilizing the LSB capacitors to obtain the last-bit, the proposed switching scheme could decrease the area of capacitive DAC. Moreover, by modifying the switching behaviors of the most significant bit (MSB) and 2nd-MSB, the conversion rate could be improved. The prototype SAR ADC fabricated in 0.18 mu m CMOS achieves 53.68 dB SNDR and 62.85 dB SFDR at 100 MS/s sampling rate. The active area of the core is 0.216 mm(2). It consumes 5.23 mW with 1.8 V supply, resulting in a Walden figure of merit (FoM) of 123.2 fJ/conversion step.
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  • An encapsulated packet-selection routing for network on chip

    Liu, Lu   Ma, Rui   Zhu, Zhangming  

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  • An active dry electrode ecg interface circuit for wearable sensors

    Yang, Yintang   Yang, Zheng   Zhu, Zhangming   Wang, Jingmin  

    A high performance active dry electrode interface circuit for ECG signal monitoring in 0.18 mu m CMOS process is presented in this paper. AC-coupled core amplifier, input impedance boost loop and CMFB (Common-mode Feedback) circuit are applied in this analog front-end circuit. The programmable gain of the core amplifier is set from 12 dB to 40 dB. With the input impedance boost loop, a constant 2.4 GO input impedance is achieved (0.1-150 Hz @ typical condition). CMFB circuit is utilized to reduce common-mode interference, and the CMRR reaches 85 dB with the configuration of ac gain 40 dB. In this design, amplifier-based active dry electrode is utilized, which achieves better noise performance than buffer-based active electrode.
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  • A Fault-Tolerant Deflection Routing for Network-on-Chip

    Zhou, Xiaofeng   Liu, Lu   Zhu, Zhangming  

    Network-on-Chip (NoC) has become a promising design methodology for the modern on-chip communication infrastructure of many-core system. To guarantee the reliability of traffic, effective fault-tolerant scheme is critical to NoC systems. In this paper, we propose a fault tolerant deflection routing (FTDR) to address faults on links and router by redundancy technique. The proposed FTDR employs backup links and a redundant fault-tolerant unit (FTIJ) at router-level to sustain the traffic reliability of NoC. Experimental results show that the proposed FTDR yields an improvement of routing performance and fault-tolerant capability over the reported fault-tolerant routing schemes in average flit deflection rate, average packet latency, saturation throughput and reliability by up to 13.5%, 9.8%, 10.6% and 17.5%, respectively. The layout area and power consumption are increased merely 3.5% and 2.6%.
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  • 99.2% energy saving and high-linearity switching method for SAR ADCs

    Zhang, Jin   Ding, Ruixue   Zhu, Zhangming  

    A high energy saving and high linearity switching method of successive approximation register analogue-to-digital converters is presented. Based on the third reference voltage V (cm) and split-MSB switching procedure, the proposed switching scheme achieves 99.2% less switching energy and 75% less number of capacitors over the conventional architecture. Moreover, the proposed scheme also achieves DNL and INL only 0.117LSB and 0.144LSB, respectively.
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  • Analysis and optimal distribution scheme for SAR-VCO ADCs

    Ding, Ruixue   Liang, Hongzhi   Liu, Shubin   Zhu, Zhangming  

    A two-stage SAR-VCO ADC is typically implemented by a coarse SAR ADC (Successive Approximation Register Analog-to-Digital Convertor) and a fine voltage-controlled oscillator (VCO) based ADC. This structure is compatible with the low power and the inherent noise shaping of VCO-based ADC, which is used to quantize the residue of SAR. Based on the analysis of SAR-VCO ADC quantification procedure, this paper summarizes the impact of the stage resolution on performance of SAR-VCO ADCs by taking into consideration all interactions during the linearity, phase noise, energy dissipation and area. According to the results of behavioral modeling and simulation, the optimal resolution distribution of SAR-VCO ADC as6-bit SAR and 4-bit VCO quantization can be obtained.
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  • A current-reuse dual-channel bio-signal amplifier for WBAN nodes

    Liu, Lianxi   Zhang, Yi   Song, Yu   Zhu, Zhangming   Yang, Yintang  

    This paper presents a dual-channel low-noise bio-signal amplifier for the low-power wireless body area network (WBAN) nodes. A dual-channel three-input current-reuse (DTCR) structure is proposed to optimize the noise performance of amplifier. The chopper-stabilized technique is employed to reduce 1/f noise and the offset voltage. Moreover, a high input impedance is achieved by using the pre-charge technique. In addition, a DC offset canceling loop is employed to suppress the electrode offset. The proposed amplifier is implemented in a standard 0.18 mu m CMOS process with an active area of about 0.68 x 0.73 mm(2). The experimental results demonstrate that an input referred noise of 1.12 mu V-rms has been achieved over a bandwidth from 0.35 Hz to 150 Hz. The total power consumption of each channel is about 1.44 mu W at the supply voltage of 1.2 V. And the amplifier achieves an input impedance of about 200 M Omega, a CMRR of 111 dB at 50 Hz and a PSRR of 87.5 dB at 50 Hz.
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