This paper presents a five-level flying capacitor multilevel (FCML) converter with an integrated auxiliary power converter to supply power to the controller and gate drive circuitry. The auxiliary power converter is sourced from within the FCML converter at a naturally occurring low-voltage node, reducing the voltage rating requirements by 75% and thus the size of the auxiliary converter. The auxiliary load current drawn from the FCML converter induces an imbalance in the flying capacitors, which is detrimental to the capacitor and switch ratings if left unchecked. To compensate for this imbalance, an active-balancing method is proposed that adjusts the phase and duty cycle of the traditional phase-shifted pulsewidth modulated control signals. The active balancing requires only a single capacitor voltage measurement and proportional control with no additional hardware components. A start-up circuit is proposed to power the auxiliary power supply and soft-start the FCML converter. Experimental results have been demonstrated with an experimental prototype resulting in an excellent flying capacitor balancing and FCML start-up.

The series-stacked architecture provides a method to increase power delivery efficiency to multiple processors by leveraging the inherent voltage step-down properties of series-connected elements. With a series stack, differential power processing (DPP) is needed to ensure that processor voltages remain within design limits, as the individual loads vary. This paper demonstrates a switched-capacitor (SC) converter to balance a stack of four ARM Cortex-A8-based embedded computers. We investigate hard-switched and resonant modes of operation in a ladder SC DPP converter implemented with GaN transistors. Operation within supply limits of each embedded computer is demonstrated in a four-series-stack configuration with realistic computational workloads. Moreover, we demonstrate hot-swapping of individual computers with maintained voltage regulation at all nodes. A peak stack power delivery of 99% is experimentally measured, and DPP switching frequencies from 200 kHz to 2 MHz are demonstrated.

One of the challenges of utilizing flying capacitor multi-level (FCML) converters is the flying capacitor balancing. Poorly balanced flying capacitors increase the switch voltage stress, which is detrimental to performance and device rating requirements. Previously, valley current detection was shown as a potential method to balance flying capacitors, but the method suffers from poor flying capacitor balancing performance at light load. Here, we investigate the light load conditions that lead to poor balancing and propose a new method, constant effective duty cycle (CEDC) compensation, which provides active balancing for the full load range of the converter. The proposed method is validated with a 4-level FCML experimental prototype, demonstrating excellent flying capacitor balancing over all load ranges, across the full duty cycles range and with multiple induced flying capacitor imbalances.