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Now showing items 1 - 16 of 33

  • Switching-Time Dependent PUF Using STT-MRAM

    Kumar, Ashwani   Sahay, Shubham   Suri, Manan  

    Physically Unclonable Function (PUF) has become an indispensable on-chip security primitive for hardware security. Area and power efficient PUFs are required to sustain the future security of IoT platforms. In particular, emerging magneto-resistive STT-MRAM based PUF circuits have gained much attention as an alternative to software/pure CMOS PUF owing to their area and power efficiency. In this work, we propose a novel PUF extraction architecture and methodology that exploits the probabilistic switching behavior of STT-MRAM devices. We exploit spatial (device to device) as well as temporal (cycle to cycle) switching stochasticity of STT-MRAM devices in an array of 1T-1MTJ cells. We performed all simulations using 90 nm CMOS technology node, and 32 nm (diameter) perpendicular anisotropic magnetic tunnel junction (PMA-MTJ). The proposed PUF exhibits 45.83 % inter-hamming distance and similar to 5.0 % intra-hamming distance without post processing of the extracted bit pattern.
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  • OxRAM RNG Circuits Exploiting Multiple Undesirable Nanoscale Phenomena

    Sahay, Shubham   Kumar, Ashwani   Parmar, Vivek   Suri, Manan  

    Compact, low-power random number generators (RNG) are essential for applications such as stochastic-, bioinspired-computing, data-encryption, cryptography in communication and security systems. We demonstrate two highly scalable hybrid CMOS-OxRAM RNG implementations based on single OxRAM and 2-OxRAM -circuits. We show how multiple undesirable nanoscale OxRAM phenomena, such as reset-current fluctuation, random telegraph noise (RTN), and reset-state resistance variability in HfOx devices can be coupled to realize RNGs. We show that mitigation of history (memory) effect in 2-OxRAM RNGs can be achieved by using optional OxRAM switching and smaller sampling frequency. Using circuit simulations with calibrated compact models, the proposed hybrid RNG circuits have been validated for 10 nm thick HfOx devices and 180 nm CMOS node. RNG performance is characterized using chi-square test, serial spectral test, and covariance/correlation-based analysis.
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  • Nanotube Junctionless FET: Proposal, Design, and Investigation

    Sahay, Shubham   Kumar, Mamidala Jagadesh  

    In this paper, we propose a nanotube (NT) JLFET for significantly improved performance in the sub-10-nm regime. We show that the tunneling width at the channel-drain interface and the source-to-channel barrier height are considerably increased in the NT JLFET due to the presence of the core gate. Therefore, the lateral band-to-band-tunneling-induced parasitic bipolar junction transistor action is diminished in the off-state of NT JLFET, leading to a significantly high on-state to off-state current ratio of similar to 10(7) even for a channel length of 7 nm. Furthermore, we demonstrate that the spacer length and dielectric constant and the core gate diameter can be used as design parameters to further improve the performance of the NT JLFETs. Therefore, we also provide the necessary design guidelines for NT JLFETs.
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  • OxRAM RNG Circuits Exploiting Multiple Undesirable Nanoscale Phenomena

    Sahay, Shubham   Kumar, Ashwani   Parmar, Vivek   Suri, Manan  

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  • Nanotube Junctionless FET: Proposal, Design, and Investigation

    Sahay, Shubham   Kumar, Mamidala Jagadesh  

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  • Realizing Efficient Volume Depletion in SOI Junctionless FETs

    Sahay, Shubham   Kumar, Mamidala Jagadesh  

    In this paper, we provide a simple and effective solution to realize efficient volume depletion and therefore, significantly reduce the OFF-state leakage current of a junctionless FET (JLFET) by replacing the SiO2 by HfO2 in the buried oxide (BOX). Using calibrated 2-D simulations, we show that the JLFET with a high-k BOX (HB JLFET) exhibits a considerably high I-ON/I-OFF ratio of similar to 10(6) even for a channel length of 20 nm. Further, we demonstrate that the use of a high-k BOX leads to a reduction in both gate capacitance C-g and gate-to-drain feedback (Miller) capacitance C-gd.
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  • Insight into Lateral Band-to-Band-Tunneling in Nanowire Junctionless FETs

    Sahay, Shubham   Kumar, Mamidala Jagadesh  

    In this paper, we investigate the nature of lateral band-to-band-tunneling (L-BTBT) component of gate-induced drain leakage (GIDL) in different nanowire junctionless FET (NWJLFET) configurations for the first time. Although the NW junctionless accumulation mode (JAM) FET has a larger ON-state current compared with the NWJLFETs, we demonstrate that the L-BTBT GIDL is larger in the NWJAMFET compared with the NWJLFET. Furthermore, we explore for the first time the application of a dual-material gate (DMG) in the NWJAMFET to suppress the L-BTBT GIDL. Using calibrated 3-D simulations, we show that the OFF-state current in the DMG NWJAMFET is reduced significantly by six orders of magnitude leading to a considerable ON-state to OFF-state current ratio (I/I-OFF) of similar to 10(10). Furthermore, the DMG NWJAMFET offers: 1) an enhanced ON-state current and 2) a significantly reduced OFF-state current compared with the NWJLFETs. Furthermore, we also demonstrate that the DMG NWJAMFET exhibits a higher transconductance than the single material gate NWJAMFET in the saturation region. In addition, we also show that there is a tradeoff between the off-state current and the intrinsic delay and the cut-off frequency in the DMG NWJAMFET. Therefore, we provide the design guidelines for appropriately choosing the work functions of the dual gates and the ratio of the length of the dual gates to the total gate length.
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  • Realizing Efficient Volume Depletion in SOI Junctionless FETs

    Sahay, Shubham   Kumar, M. Jagadesh  

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  • Efficient Mixed-Signal Neurocomputing Via Successive Integration and Rescaling

    Bavandpour, Mohammad   Sahay, Shubham   Mahmoodi, Mohammad R.   Strukov, Dmitri  

    The widespread and ever-increasing demand for performing in situ inference, signal processing, and other computationally intensive applications in mobile Internet-of-Things (IoT) devices requires fast, compact, and energy-efficient vector-by-matrix multipliers (VMMs). The time-domain VMMs based on emerging nonvolatile memory devices exhibit significantly higher circuit density and energy efficiency than their current-mode counterparts. However, the load capacitors used to accumulate the weighted summation of the inputs in the time-domain-based circuits dominate their energy dissipation and footprint area. The true potential of the time-domain-based VMMs may be realized only when this overhead is minimized. To this end, in this brief, we propose a novel successive integration and rescaling (SIR) approach for implementing a highly efficient mixed-signal time-domain VMM for low-to-medium-precision computing. For a proof of concept, we quantitatively evaluated the performance of the proposed SIR VMM and compared it with the results of the conventional time-domain VMM, using a similar 1T-1R array. Preliminary simulation results for the 4-bit $200\, \times \, 200$ VMM, implemented using a 55-nm technology node, show area and energy efficiencies of 1.33 bits/m(2) and similar to 1.3 POp/J-the numbers, respectively, $\sim 2.5\times $ and $\sim 2.65\times $ higher than those for the prior-work time-domain VMM. Furthermore, we analyze the system-level performance of the proposed SIR VMM engine in the neuromorphic accelerator architectures and provide the preliminary estimates for various deep/recurrent neural network (DNN/RNN) applications.
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  • A Behavioral Compact Model for Static Characteristics of 3D NAND Flash Memory

    Sahay, Shubham   Strukov, Dmitri  

    We present a behavioral compact model for static characteristics of 3D NAND flash memory for integrated circuits and system-level applications utilizing BSIM-CMG 110.0.0. This model is easy to implement, computationally efficient, fast, accurate, and effectively accounts for the different parasitic capacitance coupling effects applicable to the 3D geometry of the vertical channel Macaroni body charge-trap flash memory. The model parameter extraction methodology is simple and can be extended to reproduce the electrical behavior of different 3D NAND flash memory architectures (with different page size, dimension, or a number of stacked layers). We believe that the developed compact model would equip the circuit designers and system architects with an effective tool for design-exploration of 3D NAND flash memory devices for diverse unconventional analog applications.
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  • A Behavioral Compact Model for Static Characteristics of 3D NAND Flash Memory

    Sahay, Shubham   Strukov, Dmitri  

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  • Spacer Design Guidelines for Nanowire FETs From Gate-Induced Drain Leakage Perspective

    Sahay, Shubham   Kumar, Mamidala Jagadesh  

    In this paper, we study for the first time the impact of the design of gate sidewall spacer on the gate-induced drain leakage (GIDL) of: 1) the conventional nanowire (NW) FETs and 2) NWFETs with a gatesource/drain extension underlap. We demonstrate that the inclusion of a high-kappa spacer over the source/drain extension region in the conventional NWFETs results in a suppressed lateral band-to-band tunneling (L-BTBT) GIDL. Furthermore, we also show that a gate-source/drain extension underlap architecture in NWFETs not only reduces the transverse BTBT GIDL but also mitigates the L-BTBT. However, the inclusion of a high-kappa spacer in the underlapped NWFET leads to an enhanced L-BTBT and an increased off-state current compared with the underlapped NWFET with air spacer unlike FinFETs. In addition, we also study the impact of nanowire diameter and underlap length on L-BTBT GIDL of NWFETs. Furthermore, we demonstrate that the inclusion of the high-kappa spacer increases the intrinsic delay owing to an increased fringe capacitance. Therefore, we provide the necessary design guidelines for performance optimization of NWFETs in the sub-10-nm regime.
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  • Spacer Design Guidelines for Nanowire FETs From Gate-Induced Drain Leakage Perspective

    Sahay, Shubham   Kumar, Mamidala Jagadesh  

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  • A Novel Gate-Stack-Engineered Nanowire FET for Scaling to the Sub-10-nm Regime

    Sahay, Shubham   Kumar, Mamidala Jagadesh  

    In this paper, we propose a novel dual-metal gatestack (DMSG) architecture with HfO2 spacer for scaling the nanowire FETs (NWFETs) to the sub-10-nm regime. We demonstrate that the electric field at the channel-drain extension interface is reduced when the inbuilt electric field arising due to a difference in the work function at the interface of the two metals in the DMSG is coupled to the nanowire through the fringing fields through the HfO2 spacer. The reduction in the electric field leads to a larger tunneling width, and therefore suppresses the lateral band-to-band-tunneling component of the gate-induced drain leakage in the DMSG NWFETs. Although the gate capacitance increases in the DMSG NWFETs due to the fringing fields, this paper demonstrates that the increase in the intrinsic delay (similar to 1.5 times) is not very significant to degrade the circuit performance drastically. Using calibrated 3-D simulations, we show that the off-state current is reduced by more than five orders of magnitude in the DMSG NWFETs, leading to a significantly high on-state to off-state current ratio of similar to 10(6) even when the channel length is scaled to 7 nm.
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  • Diameter Dependence of Leakage Current in Nanowire Junctionless Field Effect Transistors

    Sahay, Shubham   Kumar, Mamidala Jagadesh  

    In this paper, we give a physical insight into the diameter-dependent dominant leakage mechanisms in the nanowire junctionless (NWJL) FETs. Using calibrated 3-D simulations, we show that the off-state current in the NWJLFETs with nanowire diameter less than 10 nm is governed by the drain-induced barrier lowering and the consequent source-to-channel barrier height and barrier thinning, which controls the lateral band-to-band tunneling (L-BTBT)-induced parasitic bipolar junction transistor (BJT) action. Furthermore, the quantum confinement-induced bandgap enhancement is shown to lower the probability of L-BTBT, and hence acts as the dominant mechanism in reducing the off-state current of the NWJLFETs with sub-7 nm diameter. In addition, the hole accumulation due to L-BTBT induces a shielding effect, which results in an inefficient volume depletion, leading to a large off-state current in NWJLFETs with nanowire diameters >15 nm. Furthermore, the impact of gate sidewall spacer on the L-BTBT-induced parasitic BJT in NWJLFETs has also been investigated.
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  • A Novel Gate-Stack-Engineered Nanowire FET for Scaling to the Sub-10-nm Regime

    Sahay, Shubham   Kumar, Mamidala Jagadesh  

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