Creat membership Creat membership
Sign in

Forgot password?

Confirm
  • Forgot password?
    Sign Up
  • Confirm
    Sign In
home > search

Now showing items 1 - 16 of 39

  • A monolithic K-band phase-locked loop for microwave radar application

    Zhou, Guangyao   Ma, Shunli   Li, Ning   Ye, Fan   Ren, Junyan  

    Download Collect
  • METHOD FOR SWITCHING DISPLAY OBJECT IN MULTI-WINDOW SYSTEM AND DEVICE THEREOF

    A method for switching a display object in a multi-window system and a device thereof, for addressing the problem of not switching a window on the basis of an input event, the method comprises: obtaining a coordinate value of a touched point comprised in an input event (41); determining whether the display object corresponding to a touchable region comprising the coordinate value is a topmost display object (42); if the result is determined to be NO, setting the display object as the topmost display object, and refreshing a display interface (43).
    Download Collect
  • A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic

    Ni, Zhekan   Chen, Yongzhen   Ye, Fan   Ren, Junyan  

    Download Collect
  • Pasting and thermal properties of waxy corn starch modified by 1,4-α-glucan branching enzyme

    Ren, Junyan   Li, Yang   Li, Caiming   Gu, Zhengbiao   Cheng, Li   Hong, Yan   Li, Zhaofeng  

    Download Collect
  • HIGH-SPEED PIPELINED SUCCESSIVE APPROXIMATION ADC BASED ON DYNAMIC RINGING-BASED OPERATIONAL AMPLIFIER

    A high-speed pipelined successive approximation ADC based on a dynamic ringing-based operational amplifier comprises: a pipelined quantization front end (301), configured to realize quantization of higher-order bits in the ADC, wherein the pipelined quantization front end (301) is provided with a dynamic ringing-based residue amplifier (307) configured to perform residue amplification; a remainder quantization rear end (302), composed of two successive approximation ADC sub-channels (308, 309) and configured to realize comparison and quantization of lower-order bits in the ADC, wherein input ends of the two successive approximation ADC sub-channels (308, 309) are respectively connected to output ends of the dynamic ringing-based residue amplifier (307); and a digital selection and redundant bit correction module (303) connected to output ends of the two successive approximation ADC sub-channels (308, 309) and configured to realize digital output selection, digital output time alignment, and redundant bit correction for the dual-channel time-interleaved successive approximation ADC. The above technical solution has advantages of a high speed and low power consumption when compared with a conventional pipelined successive approximation ADC, thereby reducing the static power consumption of an inter-stage residue amplifier.
    Download Collect
  • PAGE SWITCHING METHOD AND DEVICE

    A page switching method and device, which are used for improving the page switching efficiency. The method comprises: receiving a switching instruction, the switching instruction carrying a page identifier of a covered page (S301); adjusting the location of a page content corresponding to the page identifier in a stack, so that the page content corresponding to the page identifier is located at the stack top of the stack (S302); and displaying the page content at the stack top (S303). In this way, so long as a switching instruction is received, a page content corresponding to a page identifier carried in the switching instruction is adjusted to the stack top from other storage region of a stack, and the page content at the stack top is directly displayed, that is, a covered page is directly displayed to a user. Therefore, the page switching efficiency can be effectively improved.
    Download Collect
  • A High-Isolation Eight-Way Power Combiner

    Guo, Letian   Li, Jiawei   Huang, Wenhua   Shao, Hao   Xie, Shaoxi   Deng, Guangjian   Zhang, Yuchuan   Ren, Junyan  

    A high-isolation eight-way power combiner is proposed in this article that is constructed by cascading three stages of power combiners in series. Its high isolation and low return loss are realized by means of lumped isolators, an isolated side network, and a resistive septum. The eight-way power combiner is basically a 17-port mode network, consisting of eight input ports, eight matching ports, and one output port. The mode network matrix cascade computation clearly reveals the working mechanism. Based on the designed 17-port network, an eight-way power combiner is realized with eight matching ports connected to loads. The measurements agree well with the simulations. From 7.8 to 10.2 GHz, the return loss at the input ports is greater than 19 dB, the return loss at the output port is greater than 18 dB, the isolation is at least 19 dB, and the insertion loss is less than 0.4 dB. The proposed eight-way power combiner has the merits of high isolation, low return loss, low insertion loss, high power capacity, and ease of integration, with great potential for integration into high-power amplifiers.
    Download Collect
  • Design of low-power, 1 GS/s throughput FFT processor for MIMO-OFDM UWB communication system

    Liu, Liang   Ren, Junyan   Wang, Xuejing   Ye, Fan  

    A new 8PBF structure for 64/128 flexible point FFT processor is proposed. The processor, which is based on 8*8*2 mixed radix algorithm, can deal with multiple inputs more efficiently for MIMO applications. The 8PFB structure efficiently brings the throughput of the processor up to 1GS/s and the chances of register reverse down, reducing the power dissipation remarkably. Meanwhile the modified shift-add algorithm can remove complex multipliers in the fit processor.
    Download Collect
  • Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial V-cm-Based Switching

    Xing, Dezhi   Zhu, Yan   Chan, Chi-Hang   Sin, Sai-Weng   Ye, Fan   Ren, Junyan   U, Seng-Pan   Martins, Rui Paulo  

    This brief presents a 7-bit 700-MS/s four-way time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC). A partial V-cm-based switching method is proposed that requires less digital overhead from the SAR controller and achieves better conversion accuracy. Compared with switchback switching, the proposed method can further reduce the common mode variation by 50%. In addition, the impacts of such a reduction on the comparator offset, noise, and input parasitic are theoretically analyzed and verified by simulation. The prototype fabricated in a 65-nm CMOS technology occupies an active area of 0.025 mm(2). The measurement results at the 700 MS/s sampling rate show that the ADC achieves signal-to-noise-and-distortion ratio of 40 dB at Nyquist input and consumes 2.72 mW from a 1.2 V supply, which results in a Walden FoM of 48 fJ/conversion step.
    Download Collect
  • A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter

    Shu, Guanghua   Guo, Yao   Ren, Junyan   Fan, Mingjun   Ye, Fan  

    This paper presents a 10-bit 40-MS/s pipelined analog-to-digital converter (ADC) in a 0.13-mu m CMOS process for subsampling applications. A simplified opampsharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency compensation is developed to achieve both high bandwidth and large swing with low power dissipation. The measured result shows that the ADC achieves over 77 dB spurious free dynamic range (SFDR) and 57.3 dB signal-to-noise-plus-distortion ratio (SNDR) within the first Nyquist zone and maintains over 70 dB SFDR and 55.3 dB SNDR for input signal up to 75 MHz. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are +/- 0.2 LSB and +/- 0.3 LSB, respectively. The ADC consumes 15.6 mW at the sampling rate of 40 MHz from a 1.2-V supply voltage, and achieves a figure-of-merit (FOM) value of 0.22 pJ per conversion step.
    Download Collect
  • Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer

    Fei, Wei   Yu, Hao   Fu, Haipeng   Ren, Junyan   Yeo, Kiat Seng  

    To provide wide frequency tuning range (FTR) with compact implementation area, a new inductive tuning method is introduced in this paper for CMOS 60 GHz voltage controlled oscillator (VCO). The inductive tuning is based on a switching inductor-loaded transformer by configuring different current return-paths in the secondary coil of the transformer. Different from previous inductive tuning methods, the proposed VCO topology can achieve wide FTR for multiple sub-bands at 60 GHz within compact area by only one transformer. Two 60 GHz VCOs are demonstrated in 65 nm CMOS with design targets for the maximum FTR and the balanced phase noise in each sub-band, respectively. As measured by experiments, the first VCO (asymmetric) achieves a wide FTR of 25.8% from 51.9 to 67.3 GHz with phase noise variation of +/-8.2 dB (-90.2 to -106.7 dBc/Hz at 10 MHz offset) in all sub-bands; and the second VCO (symmetric) realizes a low phase noise variation of -2.5 dB (-105.9 to -110.8 dBc/Hz at 10 MHz offset) in all sub-bands with a FTR of 14.2% from 57.0 GHz to 65.5 GHz.
    Download Collect
  • Design of highly-parallel, 2.2Gbps throughput signal detector for MIMO systems

    Liu, Liang   Ma, Xiaojing   Ye, Fan   Ren, Junyan  

    This paper presents a field-programmable gate array (FPGA) implementation of a new multiple-input multiple-output (MIMO) signal detection algorithm applicable to ultra-high throughput MIMO communication systems. The algorithm simplifies the computation significantly compared to traditional K-Best algorithm, and with negligible bit error ratio (BER) degradation. A highly-parallel structure is implemented on the Xilinx Virtex-4 (XC4VLX200) platform, which achieves 2.2Gbps detection throughput and is about four times over previous implementation. Moreover, a pre-processing method is realized to reduce the number of multipliers inside the detector and shrinks the critical path delay down to 6.79ns. Together with candidate-sharing-architecture to further save the hardware cost, a high speed, compact signal detector for MIMO systems is demonstrated.
    Download Collect
  • A 1-GS/s 6-bit folding and interpolating ADC in 0.13-mu m CMOS

    Lin, Li   Ren, Junyan   Zhu, Kai   Ye, Fan  

    A 1-GS/s 6-bit two-channel time-interleaved folding and interpolating analog-to-digital converter (ADC) is presented in this article. For low voltage applications, input-connection-improved active interpolating amplifiers and cascaded folding amplifiers have been applied. A single front-end track-and-hold (T/H) circuit is used to avoid the sampling-time mismatches between the channels. When supplied with 1.4 V, the circuit achieves signal-to-noise-plus-distortion ratio (SNDR) of 30.74 dB and spurious free dynamic range (SFDR) of 36.91 dB and consumes a power of 66 mW with 500-MHz input and 1-GS/s sampling rate. Differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.57 and 0.81 LSB, respectively. The figure of merit (FoM) is 1.75 pJ/conversionstep. The ADC circuit is prototyped in 0.13-mu m CMOS process and occupies a core area of 0.45 mm(2).
    Download Collect
  • A 0.13-mu m CMOS 0.1-12 GHz active balun-LNA for multi-standard applications

    Zhang, Kaichen   Li, Wei   Li, Ning   Ren, Junyan  

    A 0.1-12 GHz Low Noise Amplifier (LNA) with an active balun is proposed for multi-standard applications. In order to realize wideband matching and single-to-differential (S2D) conversion simultaneously, a single-end resistive negative feedback amplifier is adopted as the first stage for input impedance matching, and a novel active balun consisting of common source amplifier and source follower is designed as latter stage for S2D conversion. This LNA is fabricated in a 0.13- mu m CMOS process with an active area of 0.33 mm(2). The measurement results show that over the full band of interest, the LNA achieves a minimum noise figure (NF) of 3.2 dB, input reflection coefficient S11 less than -9.3 dB, a power gain (S21) of 14.1 dB and -3.6 dBm IIP3 with a power consumption of 10.8 mW from 1.2-V supply.
    Download Collect
  • A Systematic Error Model of High-Resolution Pipelined Analog-to-Digital Converters

    Chen, Tingqian   Yao, Bingkun   Xu, Jun   Ren, Junyan  

    This work presents a systematic error model of high-resolution pipelined analog-to-digital converters (ADCs) implemented in MATLAB. Many errors limit linearity or noise performance of high-resolution ADCs; such as sampling distortion; slew-rate (SR) limiting; closed-loop gain variation of amplifiers; capacitor mismatch; clock jitter and thermal noise. All errors mentioned above are analyzed and modeled in a set of explicit mathematic expressions. Simulation results based on this model are compared with measured results of a 10-bit prototype ADC.
    Download Collect
  • Pasting and thermal properties of waxy corn starch modified by 1,4-alpha-glucan branching enzyme

    Ren, Junyan   Li, Yang   Li, Caiming   Gu, Zhengbiao   Cheng, Li   Hong, Yan   Li, Zhaofeng  

    Waxy corn starch was modified with the 1,4-alpha-glucan branching enzyme (GBE) from Geobacillus thermoglucosidans STBO2. Incubating waxy corn starch with GBE increased the number of alpha-1,6 branch points and reduced the average chain length. Enzymatic modification also decreased the breakdown and setback values of Brabender viscosity curves, indicating that the modified starch had higher paste stability. Pre-heating the starch at 65 degrees C for 30 min before incubation with GBE could promote enzymatic modification of starch. Linear regression was used to describe the relationships between starch structure and its pasting and thermal properties. The setback value showed a negative linear correlation with the alpha-1,6 branch point content (R-2 =3D 0.9824) and a positive linear correlation with the average chain length (R-2 =3D 0.8954). Meanwhile, the gelatinization enthalpy was also linearly correlated to the alpha-1,6 branch point content (R-2 =3D 0.9326) and the average chain length (R-2 =3D 0.8567). These insights provide a useful reference for food processors. (C) 2017 Elsevier B.V. All rights reserved.
    Download Collect
1 2 3

Contact

If you have any feedback, Please follow the official account to submit feedback.

Turn on your phone and scan

Submit Feedback