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Now showing items 1 - 16 of 28

  • A High Gain, 808MHZ GBW Four-Stage OTA in 65nm CMOS

    Li, Zhe   Ma, Rui   Liu, Maliang   Ding, Ruixue   Zhu, Zhangming  

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  • A 12-bit 200MS/s pipeline ADC with 91 mW power and 66 dB SNDR

    Liu, Maliang   Lian, Kaixiong   Huang, Yingzhou   Ma, Rui   Zhu, Zhangming  

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  • A 67.2?dB SNDR 1.8-V 12-bit 2-MS/s SAR ADC without calibration

    Liu, Maliang   Xie, Yi   Zhu, Zhangming  

    This paper presents a 12-bit 2-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) without calibration based on 0.18 μm 1P6M CMOS technology. To gain one bit of resolution without increasing the number of capacitors, one-side-fixed technique is used to generate the proposed switching procedure based on merged capacitor switching (MCS) switching procedure. Besides, a new DAC control logic is proposed by inserting the SAR logic circuits into level-shift circuits to reduce the complexity of the DAC control logic, enable high-speed and low-power operation and reduce the chance of race and hazard of the combinational logic circuit at the same time. The measured results show the proposed ADC achieves an SNDR of 67.26 dB and consumes 183.3 μW at 1.8 V power supply and 2 MS/s, the peak DNL and INL are +0.66/−0.64 LSB and +0.75/−0.74 LSB, respectively, resulting in a figure-of-merit of 48.63 fJ/conversion-step. The ADC core occupies an active area of 630 × 570 µm2.
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  • A low distortion CMOS analogue switch with high-order compensation

    Liu, Maliang   Wang, Jingyu   Zhu, Zhangming   Guo, Wei   Liu, Lianxi   Ding, Ruixue  

    A novel bootstrapped analogue switch with high-order harmonic distortion compensation applied in the multiply digital-to-analog convertor (MDAC) of high-speed and high-resolution pipelined analog-to-digital convertor is presented. To diminish inherent harmonic distortion introduced by the bootstrapped switch, the auxiliary circuit is adopted to achieve high-order compensation. Under the appropriate design, harmonic distortion introduced by the auxiliary circuit and that introduced by the bootstrapped switch can cancel out with each other. A 1.5 bit MDAC circuit based on the proposed switch has been fabricated in SMIC 0.18 mu m CMOS process. In 10 MHz input with 100 MHz sample frequency, the signal-to-noise and distortion ratio of 102.72 dB, spurious-free dynamic range of 107.7 dB and total harmonic distortion of 106.1 dB have been measured.
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  • PN-assisted digital background calibration of two-step ADC to over 14-bit accuracy

    Liu, Maliang   Hu, Jin   Zhang, Sirui   Zhu, Zhangming  

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  • A High-SFDR 14-bit 500 MS/s Current-Steering D/A Converter in 0.18 μm CMOS

    Liu, Maliang   Zhu, Zhangming   Yang, Yintang  

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  • A Linear-array Receiver Analog Front End Circuit for Rotating Scanner LiDAR Application

    Zheng, Hao   Ma, Rui   Liu, Maliang   Zhu, Zhangming  

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  • A wideband patch antenna with a pair of antisymmetric balun as differentially fed network

    Zhang, Jianqiang   Lan, Haokun   Liu, Maliang   Yang, Yintang  

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  • A 66dB Linear Dynamic Range, 100dBΩ Transimpedance Gain TIA with High Speed PDSH for LiDAR

    Ma, Rui   Liu, Maliang   Zheng, Hao   Ma, Rui   Zhu, Zhangming  

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  • A High Linear Voltage-to-Time Converter (VTC) with 1.2V Input Range for Time-Domain Analog-to-Digital Converters

    Liu, Haizhu   Liu, Maliang   Zhu, Zhangming   Yang, Yintang  

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  • High Sensitivity and Wide Dynamic Range Analog Front-End Circuits for Pulsed TOF 4-D Imaging LADAR Receiver

    Zheng, Hao   Ma, Rui   Liu, Maliang   Zhu, Zhangming  

    Analog front-end (AFE) circuits, which mainly consist of a transimpedance amplifier (TIA) with wide dynamic range and a timing discriminator with double threshold voltage, were designed and implemented for a pulsed time-of-fight 4-D imaging LADAR receiver. The preamplifier of the proposed TIA adopts a shunt-feedback topology to amplify weak echo signal, and a current-mirror topology to amplify strong one, respectively. The proposed AFE can capture directly the pulsed echo amplitude with wide dynamic range through programmable gain control switches. The proposed AFE circuits, which achieve a high gain of 106 dB Omega, a linear dynamic range of 80 dB, an averaged input-referred noise density of 0.89 pA/Hz(0.5) and a minimum detectable signal of 0.36 mu A at SNR =3D 5, and a sensitivity of 8 nW with APD of 45 A/W, were designed with 3.3 V devices and fabricated in a 0.18-mu m standard CMOS process. The total area of AFE, which includes the circuit core, bandgap and bias circuits, and I/O PAD, is approximately equal to 1.20 x 1.13 mm(2).
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  • A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration

    Li, Dengquan   Zhu, Zhangming   Ding, Ruixue   Liu, Maliang   Yang, Yintang   Sun, Nan  

    This brief presents a 10-bit 600 MS/s 4-channel time-interleaved (TI) successive approximation register analog-to-digital converter (ADC). A background calibration algorithm using Lagrange polynomial interpolation is introduced to calibrate timing skew. It consists of digital detection and adaptive derivative-based correction, employing low filter taps and resulting in hardware reduction. Two reference voltage generators are implemented on-chip to provide a stable reference voltage for the sub-ADCs, enhancing the reliability and robustness of the circuits. The TI-ADC prototype is fabricated in the 65-nm CMOS process and occupies an area of 0.69 mm(2). The measurement results show that at a sampling rate of 600 MS/s the ADC achieves a 49-dB SNDR after calibration while dissipating 34 mW from a 1.2/2.5-V supply.
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  • A Handheld Nano Through-Wall Radar Locating With the Gain-Enhanced Vivaldi Antenna

    Zhang, Jianqiang   Lan, Haokun   Liu, Maliang   Yang, Yintang  

    In this work, a gain-enhanced Vivaldi antenna is proposed, which is integrated with the transceiver on a printed circuit board. The gain and the radiation pattern are improved with the addition of the optimization strips in front of the flare without extending the antenna width. Finally, conventional and gain-enhanced Vivaldi antennas are fabricated and applied to the through-wall radar(TWR) system. According to the measurement results, the gain of the proposed antenna is 3 dB higher than that of the conventional antenna in the operating frequency range from 4 to 6 GHz. Meanwhile, the gain fluctuation is more stable and the beamwidth is narrower. The testing results of different scenarios illustrate that the TWR with the gain-enhanced antenna possessed farther detection distance and higher angular resolution compared with the system using a conventional antenna. The characteristics of the high integration and miniaturization make the TWR system suitable for individuals in handheld or wearable applications.
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  • A 67.2 dB SNDR 1.8-V 12-bit 2-MS/s SAR ADC without calibration

    Liu, Maliang   Xie, Yi   Zhu, Zhangming  

    This paper presents a 12-bit 2-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) without calibration based on 0.18 mu m 1P6M CMOS technology. To gain one bit of resolution without increasing the number of capacitors, one-side-fixed technique is used to generate the proposed switching procedure based on merged capacitor switching (MCS) switching procedure. Besides, a new DAC control logic is proposed by inserting the SAR logic circuits into level-shift circuits to reduce the complexity of the DAC control logic, enable high-speed and low-power operation and reduce the chance of race and hazard of the combinational logic circuit at the same time. The measured results show the proposed ADC achieves an SNDR of 67.26 dB and consumes 183.3 mu W at 1.8 V power supply and 2 MS/s, the peak DNL and INL are +0.66/-0.64 LSB and +0.75/-0.74 LSB, respectively, resulting in a figure-of-merit of 48.63 fJ/conversion-step. The ADC core occupies an active area of 630 x 570 A mu m(2).
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  • A Low Complexity Digital Foreground Calibration Technique for CMOS Pipelined ADCs

    Liu, Maliang   Zhang, Sirui   Jin, Hu   Zhu, Zhangming   Yang, Yintang  

    A low complexity all-digital foreground calibration technique to correct linear and nonlinear errors is proposed for pipeline ADCs in this paper. This method based on the integral nonlinearity (INL) piecewise least-squares fitting improves the linearity and obtains better SNR and SFDR performance. Two switches are added to the pre-stage reference ladder to achieve an accurate measurement of the INL and DNL of the backend ADC, which reduces the calibration complexity and improves the linearity effectively. The method was applied to a 125 MS/s 14-bit pipeline ADC fabricated in a 0.18 mu m CMOS process. The raw DNL and INL were 1 LSB and 8 LSB, respectively, without calibration, but with calibration, they were respectively improved to 0.25 LSB and 2 LSB. The ADC achieved an SNR of 64.5 dB, an SFDR of 73.8 dB and a THD of 72.7 dB with a 10 MHz input signal without calibration, but after calibration these figures were improved to 72.6 dB, 87.5 dB and 86.6 dB, respectively. Its application can also be extended to SAR ADC architecture, etc.
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  • A wideband patch antenna with a pair of antisymmetric balun as differentially fed network

    Zhang, Jianqiang   Lan, Haokun   Liu, Maliang   Yang, Yintang  

    A novel singly differentially-fed microstrip patch antenna (DFMA) is proposed, which is composed of a radiating patch, a differentially-fed network with a twin antisymmetric miniaturized baluns and a ground plane for unidirectional radiation. In the differentially-fed network, the signal is coupled to the two feedlines on both sides by the two miniaturized baluns. The radiating patch is excited by the coupling feed sheet located below the radiating patch, and the coupling feed sheet is connected to the upper end of the feedline. The lower end of the feedlines is connected to the ground plane, and there is a slot on the ground of the feeding network. Due to the existence of coupling feed sheet and slot, a second nonradiating resonant is achieved, and a wideband property is obtained. Finally, the prototype of the antenna is fabricated and studied experimentally. Simulated and measured results show that the impedance bandwidth of the antenna is 30.3% (1.71-2.32GHz) for S-11<-10 dB. Besides, a stable symmetric radiation pattern is obtained with gain around 9.6 dB and cross-polarization less than -21dB, which demonstrates the designed antenna has the property of wideband, high gain and low cross polarization.
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