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Now showing items 1 - 8 of 8

  • An 8-Bit 0.333–2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS

    Li, Dengquan   Zhang, Liang   Zhu, Zhangming   Yang, Yintang  

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  • Modeling of channel mismatch in time-interleaved SAR ADC

    Li, Dengquan   Zhang, Liang   Zhu, Zhangming   Yang, Yintang  

    In a time-interleaved analog-to-digital converter (TI ADC), several individual ADCs operate in parallel to achieve a higher sampling rate. Low power consumption as well as good linearity can be obtained by applying successive approximation register (SAR) converters as sub-channel ADCs. In spite of the advantages, this structure suffers from three mismatches, which are offset mismatch, gain mismatch, and time skew. This paper focuses on a TI SAR ADC with a number of channels. The mismatch effects in the frequency domain are analyzed and the derived close form formulas are verified based on Matlab. In addition, we clarify that the standard deviation of DNL and INL of an M-channel TI ADC is reduced by a factor of compared to a single channel ADC. The formulas can be used to derive the corresponding requirements when designing a TI ADC. Our analysis process is able to inform the study of calibration algorithms.
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  • A background fast convergence algorithm for timing skew in time-interleaved ADCs

    Li, Dengquan   Zhu, Zhangming   Zhang, Liang   Yang, Yintang  

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  • A 1.4-mW 10-bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65 nm CMOS

    Li, Dengquan   Zhu, Zhangming   Ding, Ruixue   Yang, Yintang  

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  • A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration

    Li, Dengquan   Zhu, Zhangming   Ding, Ruixue   Liu, Maliang   Yang, Yintang   Sun, Nan  

    This brief presents a 10-bit 600 MS/s 4-channel time-interleaved (TI) successive approximation register analog-to-digital converter (ADC). A background calibration algorithm using Lagrange polynomial interpolation is introduced to calibrate timing skew. It consists of digital detection and adaptive derivative-based correction, employing low filter taps and resulting in hardware reduction. Two reference voltage generators are implemented on-chip to provide a stable reference voltage for the sub-ADCs, enhancing the reliability and robustness of the circuits. The TI-ADC prototype is fabricated in the 65-nm CMOS process and occupies an area of 0.69 mm(2). The measurement results show that at a sampling rate of 600 MS/s the ADC achieves a 49-dB SNDR after calibration while dissipating 34 mW from a 1.2/2.5-V supply.
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  • A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS

    Zhang, Liang   Li, Dengquan   Zhu, Zhangming   Yang, Yintang  

    This paper presents a 10-GS/s 6-bit track-and-hold amplifier (THA), which is designed for a 16 way time-interleaved successive approximation register (SAR) analog to digital converter (ADC). To extend the bandwidth, a differential source-degenerated common-source amplifier with peaking inductance is adopted as an input buffer. A switched source follower master track and-hold stage samples the 800-mV(PP) differential input signal at 10 GHz. Moreover, the THA cancels the feed-through in hold mode by a clock-controlled transistor. The proposed THA is simulated in 65-nm CMOS technology. It operates with 1.8/1.2-V supply and consumes 84.8 mW. At a sampling rate of 10 GS/s, -41-dB total harmonic distortion (THD) is achieved with input frequencies up to 5 GHz.
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  • A Dual-Supply Two-Stage CMOS Op-amp for High-Speed Pipeline ADCs Application

    Liu, Maliang   Li, Dengquan   Zhu, Zhangming  

    In this brief, a dual-supply two-stage op-amp is proposed for a 12-b 1 GS/s pipeline ADC, which is composed of a low-voltage supply pre-amplifier and a high-voltage supply amplifier. Its closed-loop bandwidth reaches to 5.2 GHz, and the phase margin is larger than 60 degrees. The closed-loop amplifier can settle to 99.95% accuracy within 230 ps, which satisfies the harsh requirements of the first-stage MDAC. The proposed op-amp was employed in a single-channel 12-b 1 GS/s pipeline ADC. The ADC is powered by 1.3 V and the op-amp is powered by dual-supply voltage of 1.3 V and 2.5 V. The ADC fabricated in 65 nm CMOS process consumes 360 mW at 1 GS/s. It achieves an SNDR of 61.9 dB and an SFDR of 72.6 dB with 30 MHz input signal, while maintaining an SNDR > 56.0 dB and SFDR > 69.0 dB in the entire 500 MHz Nyquist band.
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  • A 10-bit 100-MS/s 5.23-mW SAR ADC in 0.18-mu m CMOS

    Ma, Rui   Wang, Lisha   Li, Dengquan   Ding, Ruixue   Zhu, Zhangming  

    A 10-bit 100 MS/s energy-efficient successive-approximation analog-to-digital converter (SAR ADC) is presented in this paper. In order to improve the conversion rate and reduce power consumption as well, a modified spilt-capacitor V-cm-based switching scheme is proposed. By utilizing the LSB capacitors to obtain the last-bit, the proposed switching scheme could decrease the area of capacitive DAC. Moreover, by modifying the switching behaviors of the most significant bit (MSB) and 2nd-MSB, the conversion rate could be improved. The prototype SAR ADC fabricated in 0.18 mu m CMOS achieves 53.68 dB SNDR and 62.85 dB SFDR at 100 MS/s sampling rate. The active area of the core is 0.216 mm(2). It consumes 5.23 mW with 1.8 V supply, resulting in a Walden figure of merit (FoM) of 123.2 fJ/conversion step.
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