In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient amplification in scaled environments, and possess the benefits of efficient slew-based charging, rapid stabilization, compression-immunity (inherent rail-to-rail output swing), and performance that scales with process technology. A basic operational theory is established, and the core benefits of this technique are identified. Measured results from two separate ring amplifier based pipelined ADCs are presented. The first prototype IC, a simple 10.5-bit, 61.5 dB SNDR pipelined ADC which uses only ring amplifiers, is used to demonstrate the core benefits. The second fabricated IC presented is a high-resolution pipelined ADC which employs the technique of Split-CLS to perform efficient, accurate amplification aided by ring amplifiers. The 15-bit ADC is implemented in a 0.18 mu m CMOS technology and achieves 76.8 dB SNDR and 95.4 dB SFDR at 20 Msps while consuming 5.1 mW, achieving a FoM of 45 fJ/conversion-step.

A hybrid (analog/digital) architecture is proposed to implement a robust high-resolution delta-sigma modulator with a single-bit output. The system contains a low-order multi-bit analog noise-shaping loop, followed by a scaling block and a high-order single-bit digital modulator. The combination simplifies the realization of the analog modulator, and it allows the use of most of its full-scale input range.

A noise-shaped two-step ADC is presented in this paper. This ADC exploits residue feedback and a new capacitor/opamp sharing scheme to achieve high order noise shaping with minimal design complexity. The application of the proposed architecture in low power Delta-Sigma modulators is studied in this paper. A prototype ADC is fabricated in a 0.18 mu m CMOS process. With a 1.56 MHz bandwidth (8x OSR), 2.6 mW analog power consumption, and 1.2 V analog supply voltage, the measured dynamic range and SNDR of this prototype IC are 78 dB and 75 dB.

A hybrid delta-sigma/pipelined modulator is presented in this paper. The proposed modulator takes advantage of the high resolution and distributed pipelined quantization, and combines it with the noise shaping property of a delta-sigma modulator. As a result, gain, swing, and slew requirements of the integrators are significantly reduced. The modulator also makes use of the latency in the pipelined quantization to enhance noise shaping. These advantages lead to less power dissipation, increased stability, and higher resolution. The prototype chip is implemented in a 0.18 mu m CMOS process. With an 80 MHz clock, and an oversampling ratio of 8 (5 MHz bandwidth), the measured dynamic range and SNDR of this prototype IC are 79 dB and 75.4 dB.

Shu, Yun-Shiang
Kamiishi, Junpei
Tomioka, Koji
Hamashita, Koichi
Song, Bang-Sup

In cascaded Delta Sigma modulators (DSMs), the quantization noise of the earlier stage leaks to the output unless completely cancelled by the digital noise cancellation filter (NCF). The noise leakage is worse in the continuous-time (CT) implementation due to the poorly controlled time constant of the analog loop filter. A parameter-based continuous-time to discrete-time transform is developed to get an exact digital NCF, and the analog filter time constant is calibrated to match with the digital NCF. A binary pulse tone is injected into the quantizer to detect the filter time-constant error, and eliminated by zero-forcing its residual power based on the adaptive least-mean-square (LMS) algorithm. A 2-1-1 cascaded CT-DSM prototype in 0.18-mu m CMOS demonstrates that the spectral density of the leaked noise is lower than 10 nV/root Hz after the capacitors in the Gm-C loop filters are trimmed with 1.1% step. With a 1-V(pp) full-scale input, it achieves a dynamic range of 68 dB within 18-MHz bandwidth at an over-sampling ratio of 10. The analog core and the digital logic occupy 1.27 mm(2), and consume 230 mW at 1.8 V.

A spread-spectrum clock generator is proposed based on an in-band phase modulation. In a charge-pump phase-locked loop configuration, the input phase modulation signal is applied to the proposed charge-based discrete-time loop filter. The phase difference between the input phase modulation signal and the output clock feedback phase is sampled and applied to the control voltage of an oscillator. The loop gain of the clock generator pushes the output clock phase to accurately trace the input phase modulation signal. This article achieves 3.2% spread-spectrum modulation range and 26.51-dB spread-spectrum attenuation at 352-MHz output frequency using a 2-MHz reference frequency. The in-band modulation improves a design sensitivity, and a 298-ppm modulation range error is measured with over 140% K-VCO perturbations. This spread-spectrum clock generator is implemented in a 0.18-mu m CMOS, and achieves 951-fs(rms) period jitter while consuming 9.98 mW from a 1.8-V power supply.

This paper describes a wideband high-linearity Delta Sigma ADC. It uses noise coupling combined with time interleaving. Two versions of a two-channel time-interleaved noise-coupled Delta Sigma ADC were realized in a 0.18-mu m CMOS technology. Noise coupling between the channels increases the effective order of the noise-shaping loops, provides dithering, and prevents tone generation in all loops. Time interleaving enhances the effects of noise coupling. Using a 1.5 V supply, the device achieved excellent linearity (SFDR > 100 dB, THD = -98 dB) and an SNDR of 79 dB in a 4.2 MHz signal band.

Aiba, Yusuke
Tomioka, Koji
Nakashima, Yuta
Hamashita, Koichi
Song, Bang-Sup

Continuous-time Delta Sigma modulators (CT-DSMs) that use transistor-based G(m)-C integrators are simple but sensitive to process and temperature variations. Their performance depends heavily on the input linear range that varies widely. A CT-DSM is implemented using a triode G(m)-C integrator and a tri-level switched-capacitor digital-to-analog converter (SCDAC). A self-scaling SCDAC keeps the input signal range constant, and an adaptive input common-mode bias control enables the triode G(m) cell to operate always with its constant input linear range. The proposed G(m) cell exhibits a tuning range of +/- 15% while maintaining its linear range over the temperature variation from -30 degrees C to 85 degrees C. A 2-MHz bandwidth, fifth-order CT-DSM in 0.18 mu m CMOS samples at 128 MS/s with an over-sampling ratio of 32 (OSR = 32), occupies an active area of 0.4 mm(2), and consumes 11 mW at 1.8 V. With a -3 dB input of the full scale (400 mV), the measured dynamic range, second harmonic distortion (HD2), and third harmonic distortion (HD3) are 71, -86, and -91 dB, respectively.

Hershberg, Benjamin
Weaver, Skyler
Takeuchi, Seiji
Hamashita, Koichi
Moon, Un-Ku

An optimized memory structure； Binary Access Memory (BAM)； is presented for successive approximation applications that employ an error correction lookup table. Unlike true random-access memory； the probability of different codes occurring in a binary successive approximation access pattern is not uniformly distributed. BAM exploits this fact in several ways to reduce the number of sub-block switches； the average and worst-case access latency； and power consumption compared to a conventional SRAM lookup table. A simple technique for using BAM in an asynchronous successive approximation design is also presented.