Spatial theories identify three aspects of the environment that are used to various degrees in route-learning tasks; namely, landmarks, routes, and configurations. Although research has demonstrated sex differences in the relative predominance of each aspect in route-learning strategies, it is unclear how these sex differences correspond to route-learning abilities in a large-scale environment. The present experiment addresses this void by examining route-learning abilities in an indoor environment. Participants are taken through an unfamiliar route and instructed to find the point of origin using one of three strategies: (a) direct, (b) retrace, and (c) choice. Results reveal sex differences in route-learning abilities in the direct condition. Furthermore, a landmark-biased strategy is used more by females and is associated with better route-learning abilities. The same relationship is not found in males. These findings suggest that sex-specific patterns of relationships exist between strategy use and route-learning abilities.

An analog VLSI neural network processor was designed and fabricated for communication receiver applications. It does not require a priori estimation of the channel characteristics. A powerful channel equalizer was implemented with this processor chip configured as a four-layered perceptron network. The compact synapse cell is realized with an enhanced wide-range Gilbert multiplier circuit. The output neuron consists of a linear current-to-voltage converter and a sigmoid function generator with a controllable voltage gain. Network training is performed by the modified Kalman neuro-filtering algorithm to speed up the convergence process for intersymbol interference and white Gaussian noise communication channels. The learning process is done in the companion DSP board which also keeps the synapse weight for later use of the chip. The VLSI neural network processor chip occupies a silicon area of 4.6 mm x 6.8 mm and was fabricated in a 2-mum double-polysilicon CMOS technology. System analysis and experimental result are presented.

We report the polarized infrared reflectance of Ti4+-doped α′-NaV2O5 and an analysis of the frequency dependent conductivity. Impurity incorporation allows us to resolve a number of new rung-polarized vibrational features due to local symmetry breaking. Variable temperature measurements both above and below the charge ordering transition indicate that the majority of zone-folding modes in Ti4+ substituted α′-NaV2O5 are a subset of those in the pristine material; minute new folded modes are observed at 46 (Ea), 105 (Ea), and 636 (Eb)cm−1. We discuss our results in terms of disruption of the rung in the vicinity of the Ti4+ defect.

The design and implementation of a high-precision VLSI winner-take-all (WTA) circuit that can be arranged to process 1024 inputs are presented. The cascade configuration can be used to significantly increase the competition resolution and maintain high-speed operation for a large-scale network. The total bias current increases in proportion to the number of circuit cells so that a nearly constant response time is achieved. A unique dynamic current steering method is used to ensure that only a single winner exits in the final output. Experimental results for a prototype chip fabricated in a 2-mum CMOS technology show that a cell can be a winner if its input is larger than those of the other cells by 15 mV. The measured response time is around 50 ns at a 1-pF load capacitance. This analog winner-take-all circuit is a key module in the competitive layer of self-organizing neural networks