IEEE Transactions on Microwave Theory and Techniques
Issue Date:
2015
Abstract(summary):
A low-voltage and low-power 50/100-GHz transformer-based phase-locked loop (PLL) is implemented in a 65-nm CMOS technology. Consuming only 14.1 mW from a 0.6/1.2-V supply, the PLL measures phase noise of -90/-84 dBc/Hz at 100-kHz offset and -94/-88 dBc/Hz at 1-MHz offset at 49.7/99.4 GHz while occupying a core chip area of 0.39 mm. Moreover, with an embedded phase shifter, the PLL output phase can be shifted by a 360 degrees range with an average resolution of 3.9 and amplitude variation less than +/- 0.1 dB, which makes it suitable for phased-array transceivers.
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