[IEEE 19th International Symposium on Power Semiconductor Devices and IC's - Jeju, Korea (2007.05.27-2007.05.31)] Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC's - Trench-Isolated High-Voltage IC with Reduced Parasitic Bipolar Transistor Action

Author:

Takahashi, Tetsuo   Terashima, Tomohide   Moritani, Junichi   

Issue Date:

2007

Abstract(summary):

For high-voltage IC device, one of the important issues is to prevent parasitic transistor acting, especially in Junction-Isolation (JI) device. In addition to this problem, it is necessary to achieve it by a minimum cost. In this paper, we propose junction-isolated HVIC using deep trench-isolation techniques. And we examined about structures of reducing parasitic transistor action by simulation and experiments. In proposed structures, the area of isolation is reduced to 2/3 to 1/2 compared with conventional junction isolation. Moreover, significant reduction of hFE of parasitic transistor in logic transistors and HV-transistor are confirmed.