This letter presents a 12-GHz wideband fractionalN phase-locked loop (PLL) with a robust voltage-controlled oscillator (VCO). The proposed PLL uses a class-C VCO with an amplitude-adjustment circuit (AAC) to increase current during the startup process and stabilize the VCO amplitude. In order to make the circuit more compact, the control logic in the VCO is simplified. A prototype of the PLL implemented in 65-nm CMOS, with an active area of 1.5 mm2, can achieve -106 dBc/Hz phase noise (PN) at 1-MHz offset from a 11.96-GHz carrier. It draws 18.2-mW power with 48-MHz reference frequency from a 1.2-V supply.
Page:
397---399
Related
Batch download
Cited By
noting
Similar Literature
Submit Feedback
Please wait while the file you selected is being converted