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A 0.5-V 5.9-fJ/Conversion-Step SAR ADC in 0.18-mu m CMOS

Author:
Ren, Xiaojiao  Zhuang, Yiqi  Li, Xiaoming  Qi, Zengwei  Wang, Bo  


Journal:
IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING


Issue Date:
2016


Abstract(summary):

In this paper, we present a 434-nW 8-bit successive approximation register analog-to-digital converter (SAR ADC). We mainly consider the optimization of power consumption. A modified split-capacitor array involving a novel switching scheme is proposed, which reduces the switching power consumption to just 13.8 CVref2 for the single-ended scheme without any losses in performance. Based on the SMIC CMOS 0.1 mu m EEPROM 2P4M process, the simulation results show that at 0.5 V supply voltage, 300 kS/s sample frequency, and 4.98 kHz input frequency, the ADC achieves an signal-to-noise-plus-distortion ratio (SNDR) of 49.58 dB and effective number of bits (ENOB) of 7.94, and consumes 434 nW, resulting in a figure of merit of 5.9 fJ/conversion step. (C) 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.


Page:
467---473


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