Creat membership Creat membership
Sign in

Forgot password?

Confirm
  • Forgot password?
    Sign Up
  • Confirm
    Sign In
Creat membership Creat membership
Sign in

Forgot password?

Confirm
  • Forgot password?
    Sign Up
  • Confirm
    Sign In
Collection

toTop

If you have any feedback, Please follow the official account to submit feedback.

Turn on your phone and scan

home > search >

Morphology Improvement of Step Bunching on 4H-SiC Wafers by Polishing Technique

Author:
Kato, Tomohisa   Kinoshita, Akimasa   Wada, Keisuke   Nishi, Takashi   Hozomi, Eiji   Taniguchi, Hiroyoshi   Fukuda, Kenji   Okumura, Hajime  


Journal:
Materials Science Forum


Issue Date:
2010


Abstract(summary):

In this paper, we report a new polishing technique regarding the elimination of step bunching on the silicon carbide (SiC) surface. The step bunching generation is often observed as frequent phenomenon on the surface of SiC epilayers grown on low off-angle (0001) SiC wafers and on SiC devices after annealing to activate the dopants. We polished the step bunching surface using a chemical mechanical polishing (CMP) technique reported in a previous study, and we succeeded to improve the morphology with a flat and smooth surface which showed a small Rms value of around 0.1nm. We especially found an excellent polishing effect for the control of leakage current in reverse I-V characteristics of SiC Schottky barrier diodes (SBD).


Page:
763-765


Similar Literature

Submit Feedback

This function is a member function, members do not limit the number of downloads