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A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications

Author:
Meng-Fan Chang   Shi-Wei Chang   Po-Wei Chou   Wei-Cheng Wu  


Journal:
IEEE Journal of Solid-State Circuits


Issue Date:
2011


Abstract(summary):

SRAM suffers read-disturb and write failures at a low supply voltage, especially at deep subthreshold operation. This study proposes a 9T-SRAM cell with a data-aware-feedback-cutoff (DAFC) scheme to enlarge the write margin and dynamic-read-decoupled (DRD) scheme to prevent read-disturb for achieving deep subthreshold operation. A 30 mV negative-pumped wordline scheme is employed to suppress bitline leakage current. The fabricated 90 nm 32 Kb 9T-SRAM macro achieves 130 mV VDDmin. All the 32 Kb 9T cells are stable across read and write operations when operated at 105 mV.


Page:
0-529


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