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A junctionless tunnel field effect transistor with low subthreshold slope

Author:
Ghosh, Bahniman  Bal, Punyasloka  Mondal, Partha  


Journal:
JOURNAL OF COMPUTATIONAL ELECTRONICS


Issue Date:
2013


Abstract(summary):

we demonstrate the design of a triple gate n-channel junctionless transistor that we call a junctionless tunnel field effect transistor (JLTFET). The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. Simulation shows significant improvement compared to simple junctionless field effect transistor both in I (ON)/I (OFF) ratio and subthreshold slope. Here, junctionless tunnel field effect transistors with high-k dielectric and low-k spacers are demonstrated through simulation and shows an ON-current of 0.25 mA/mu m for the gate voltage of 2 V and an OFF current of 3 pA/mu m (neglecting gate leakage). In addition, our device shows optimized performance with high I (ON)/I (OFF) (similar to 10(9)). Moreover, a subthreshold slope of 47 mV/decade is obtained for a 50 nm gate length of simulated JLTFET at room temperature which indicates that JLTFET is a promising candidate for switching performance.


Page:
428---436


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