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A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter

Author:
Shu, Guanghua  Guo, Yao  Ren, Junyan  Fan, Mingjun  Ye, Fan  


Journal:
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING


Issue Date:
2011


Abstract(summary):

This paper presents a 10-bit 40-MS/s pipelined analog-to-digital converter (ADC) in a 0.13-mu m CMOS process for subsampling applications. A simplified opampsharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency compensation is developed to achieve both high bandwidth and large swing with low power dissipation. The measured result shows that the ADC achieves over 77 dB spurious free dynamic range (SFDR) and 57.3 dB signal-to-noise-plus-distortion ratio (SNDR) within the first Nyquist zone and maintains over 70 dB SFDR and 55.3 dB SNDR for input signal up to 75 MHz. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are +/- 0.2 LSB and +/- 0.3 LSB, respectively. The ADC consumes 15.6 mW at the sampling rate of 40 MHz from a 1.2-V supply voltage, and achieves a figure-of-merit (FOM) value of 0.22 pJ per conversion step.


Page:
95---102


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