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Low-Noise Fractional-N PLL Design with Mixed-Mode Triple-Input LC VCO in 65nm CMOS

Author:
Sun, Yuanfeng  Yu, Xueyi  Rhee, Woogeun  Ko, Sangsoo  Choo, Wooseung  Park, Byeong-Ha  Wang, Zhihua  


Journal:
2010 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS RFIC SYMPOSIUM


Issue Date:
2010


Abstract(summary):

This paper presents a low-noise Sigma Delta fractional-N PLL utilizing a mixed-mode triple-input LC VCO. An analog dual-path VCO control relaxes the nonlinearity problem of the Sigma Delta fractional-N PLL, while a combination of discrete and continuous tuning methods for coarse-tuning control significantly alleviates the noise coupling problem caused by the high gain coarse-tuning path. A 3.6GHz Sigma Delta fractional-N PLL implemented in 65nm CMOS exhibits nearly -100dBc/Hz in-band noise contribution and -53dBc in-band fractional spur performances from a 1.8GHz carrier.


Page:
61---64


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