Low Gain Avalanche Detectors (LGADs) are based on a n(++)-p(+)-p-p(++) structure where appropriate doping of multiplication layer (p(+)) leads to high enough electric fields for impact ionization. Operation of these detectors in harsh radiation environments leads to decrease of gain attributed to the effective acceptor removal in the multiplication layer. In order to cope with that devices were produced where boron was replaced by gallium. The initial radiation hardness studies show a smaller degradation of gain with neutron fluence indicating that gallium is more difficult to displace/deactivate from the lattice site than boron.

The ATLAS Forward Proton (AFP) detector is designed to identify events in which one or two protons emerge intact from the LHC collisions. AFP will consist of a tracking detector, to measure the momentum of the protons, and a time of flight system to reduce the background from multiple proton-proton interactions. Following an extensive qualification period, 3D silicon pixel sensors were selected for the AFP tracker. The sensors were produced at CNM (Barcelona) during 2014. The tracker module assembly and quality control was performed at IFAE during 2015. The assembly of the first AFP arm and the following installation in the LHC tunnel took place in February 2016. This paper reviews the fabrication process of the AFP tracker focusing on the pixel modules.

In this paper, an ASIC fabricated in 180 nm CMOS technology from AMS with the very front-end electronics used to readout LGAD sensors is presented as well as its experimental results. The front-end has the typical architecture for Si-strip readout, i.e., preamplification stage with a Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper. Both amplifiers are based on a folded cascode structure with a PMOS input transistor and the shaper only uses passive elements for the feedback stage. The CSA has programmable gain and a configurable input stage in order to adapt to the different input capacitance of the LGAD sensors (pixelated, short and long strips) and to the different input signal (depending on the gain of the LGAD). The fabricated prototype has an area of 0.865mm x 0.965 mm and includes the biasing circuit for the CSA and the shaper, 4 analog channels (CSA+shaper) and programmable charge injection circuits included for testing purposes. Noise and power analysis performed during simulation fixed the size of the input transistor to W/L =3D 860 mu m/0.2 mm. The shaping time is fixed by design at 1 us and, in this ASIC version, the feedback elements of the shaper are passive, which means that the area of the shaper can be reduced using active elements in future versions. Finally, the different gains of the CSA have been selected to maintain an ENC below 400 electrons for a detector capacitor of 20 pF, with a power consumption of 150 mu W per channel.

In this paper we present the design and performance of a perforated thermal neutron silicon detector with a (LiF)-Li-6 neutron converter. This device was manufactured within the REWARD project workplace whose aim is to develop and enhance technologies for the detection of nuclear and radiological materials. The sensor perforated structure results in a higher efficiency than that obtained with an equivalent planar sensor. The detectors were tested in a thermal neutron beam at the nuclear reactor at the Instituto Superior Tecnico in Lisbon and the intrinsic detection efficiency for thermal neutrons and the gamma sensitivity were obtained. The Geant4 Monte Carlo code was used to simulate the experimental conditions, i.e. thermal neutron beam and the whole detector geometry. An intrinsic thermal neutron detection efficiency of 8.6% +/- 0.4% with a discrimination setting of 450 keV was measured.

The aim of this study was to investigate the relationship between warfarin dosage, international normalized ratio, plasma and oral fluid concentrations of warfarin, and its metabolites, namely RR/SS-and RS/SR-warfarin alcohols. Nine patients on long-term warfarin therapy (4 with stable and 5 with unstable international normalized ratio values) were longitudinally monitored for over two months by recording warfarin dosage and measuring international normalized ratio, warfarin and warfarin alcohols concentrations in oral fluid and in plasma. At equivalent dose (20-30 mg week(-1)), the international normalized ratio was in the range 2.0-2.5 and 1.5-3.1 for stable and unstable patients, respectively. Moreover, stable patients showed nearly double total and unbound plasma warfarin concentration, and nearly triple oral fluid warfarin concentrations compared to unstable patients. Correlations between warfarin dosage and total plasma concentration of warfarin (r =3D 0.65, p < 0.01) or RS/SR-warfarin alcohols (r =3D 0.66, p < 0.01), as well as between stimulated oral fluid and total plasma concentrations of warfarin (r =3D 0.72, p < 0.01) and RS/SR-warfarin alcohols (r =3D 0.95, p < 0.01) suggest that the relative changes of the oral fluid concentrations of these species may provide clinically useful information for monitoring individual patients. Follow-up data revealed that even in the absence of changes of warfarin dose, the oscillations of plasma and oral fluid of WAR and RS/SR-warfarin alcohols parallel oscillations of international normalized ratio. Due to the long delay of its biological action, monitoring the plasma concentration of warfarin might help to predict variations of international normalized ratio and prevent the risk of thrombotic or haemorrhagic events. The information collected suggests that non-invasive monitoring of warfarin in oral fluid might represent a suitable tool for this purpose. (C) 2017 Elsevier B.V. All rights reserved.

In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10-15 mum in both coordinates, low material budget <1%X 0, and the ability to withstand a background hit rate of several tens of MHz/cm 2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper. [All rights reserved Elsevier].

This paper reports on the first characterization of double sided 3D silicon radiation pixel detectors with slim edges. These detectors consist of a three-dimensional array of electrodes that penetrate into the detector bulk with the anode and cathode electrodes etched from opposite sides of the substrate. Different detectors were post-processed using the scribe-cleave-passivate (SCP) technology to make "slim edge" sensors. These sensors have only a minimal amount of inactive peripheral region, for the benefit of the construction of large-area tracker and imaging systems. The target application for this work is the use of 3D slim edge detectors for the ATLAS Forward Physics (AFP) CERN Project, where pixel detectors for position resolution and timing detectors for removal of pile up protons, will be placed as close as possible to the beam to detect diffractive protons at 220 m on either side of the ATLAS interaction point. For this reason the silicon areas should feature the narrowest possible insensitive zone on the sensor edge closest to the beam and withstand high nonuniform irradiation fluences. (C) 2013 Elsevier B.V. All rights reserved.

The proposed high luminosity upgrade of the Large Hadron Collider is expected to increase the instantaneous luminosity at the experiments interaction points by a factor of ten. The vertex detector will be the subsystem most affected by the luminosity increase, raising substantially their occupancy and radiation induced damage. To preserve the vertex physics performance under these new conditions, current pixel technologies have to be improved. Hybrid pixel sensors with double sided double type vertical electrodes (3D sensors) are becoming a mature technology for the detector layers closest to the interaction point due to their intrinsic radiation hardness. In addition, the double sided implementation of the 3D pixel technology provides some additional technical advantages with respect to the single-sided implementation. For this study, 3D pixel sensors manufactured at the Centro Nacional de Microelectronica of Barcelona (IMB-CNM) have been bonded to the PSI46 readout chip currently used by the Compact Muon Solenoid vertex detector. Detector performance before and after irradiation up to fluences of 5 x 10(15) n(eq)/cm(2) is presented. (C) 2013 Elsevier B.V. All rights reserved.

The asymmetric e(+) e(-) collider SuperB is designed to deliver a high luminosity, greater than 10(36) cm(-2) S-1, with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%. (C) 2012 Elsevier B.V. All rights reserved.

Prototypes of a new hybrid pixel detector and a high resistivity detector with short strips, developed by the VIPIX Collaboration and aimed at equipping the layer-0 of the SuperB vertex detector, have been tested in September 2011 with a 120 GeV pion beam at the SPS H6 beam line at CERN. They are placed at the center of a reference telescope consisting of six planes of silicon detector with a double-sided strip readout. Both the telescope and the detectors under test (DUT) are equipped with a custom-design, data-push digital readout. The main elements of the trigger and data acquisition system are two VME boards (EDRO) organized in a master-slave configuration and responsible for programming the front-end chips of both the telescope and the DUT. The master board distributes a global synchronization clock and the triggers to all devices, including two 3 x 3 analog-maps matrices placed behind the DUT and supplied with an independent readout. Both EDROs act as event-fragment builders. These are sent out to a remote PC for event building, buffering and storage. (C) 2012 Elsevier B.V. All rights reserved.