Résumé La compression veineuse est utilisée dans le cadre de pathologies telles que les phlébites. La compression est l’un des rares secteurs où les ventes progressent encore dans les officines. Les différents fabricants innovent continuellement, proposant de nouveaux coloris et de nouvelles matières. Ces dispositifs, pour être pris en charge par les organismes de sécurité sociale, doivent répondre à un cahier des charges précis et notamment respecter le niveau de compression affichée. Summary Vein compression is used in the context of pathologies such as phlebitis. Compression is one of the rare sectors where sales are still growing in pharmacies. Manufacturers are constantly innovating, offering new colours and new materials. In order for these devices to be covered by social security organisations, they must meet precise specifications and notably respect the level of compression which they claim to offer.

Today and more tomorrow, electronic system design requires being concerned with the power issues. Currently, usual design tools consider the application power consumption after RTL synthesis. We propose in this article a FPGA design flow which integrates the power consideration at the early stages. Thus, the designer determines quickly the algorithm and architecture adequacy which respects the design specifications and the power budget.

Interconnects are now considered as the bottleneck in the design of system-on-chip (SoC) since they introduce delay and power consumption. To deal with this issue, data coding for interconnect power and timing optimization has been introduced. In today’s SoCs these techniques are not efficient anymore due to their codec complexity or to their unrealistic experimentations. Based on some realistic observations on interconnect delay and power estimation, the spatial switching technique [1] is proposed. It allows the reduction of delay and power consumption (including extra power consumption due to codecs) for on-chip buses. The concept of the technique is to detect all cross-transitions on adjacent wires and to decide if the adjacent wires are exchanged or not. Results show the spatial switching efficiency for different technologies and bus lengths. The power consumption reduction can reach up to 12%for a 5-mm bus and more if buses are longer.

Power and energy consumption is currently a critical problem in digital signal and image processing applications; the emergence of Systems-on-Chip (SoCs) makes the power analysis difficult by increasing the system heterogeneity, density and performances. To take into account this problem and efficiently focus the actions, we will first examine the main sources of the power consumption and its distribution in circuits and systems; then we will propose a non exhaustive overview of estimation and optimization methods and available tools together with the needs and perspectives in low power SoC design.

The design of Wireless Sensor Networks is a challenge； requiring to correctly balancing between performance； time； cost and energy. But the main problem with rechargeable WSNs is to predict at design time which will be the total system autonomy. Moreover； it depends on the energy harvested from the environment； and we know that weather may be very unsettled. Thus； it is crucial to design and fine scale the entire power supply chain in order to produce a robust WSN. In this article； we propose an energy estimator able to handle environment like weather parameters to estimate the system autonomy. The key innovation comes from the capability to dynamically rebuild the models all along the project evolution with real measurements on the hardware and to include weather forecasts as dynamic parameters of the DPM policy. Finally； we have experiment various configurations and compared the hardware WSN against the simulator. The results have validated the relevance of the estimator for prospecting various energy problems. By experiment； the estimator has shown that most environmental energy was wasted due to the battery charging constraints. This will foresee the opportunities of energy gains； and the definition of newer extra power modes for the Dynamic Power Management. This work contributes to the domain for WSN design methodology； energy scavenging and energy management to optimize system autonomy.

A complete methodology to estimate power consumption directly at the C-level for on-the-shelf processors is proposed. It relies on a power model of the processor that describes the consumption variations relatively to algorithmic and configuration parameters. The algorithmic parameters represent the power and quality metrics of the code and can be predicted directly from the C-algorithm with simple assumptions on the compilation. To check the algorithm performances with the application constraints without compiling, direct estimation results on the C code can be summarized on a consumption map. This method strongly reduces the design complexity in terms of number of lines to be studied and allows to spot the ’hot parts’ of the code in order to target the writing effort. Applied to a VLIW processor, the TI TMSC6201, the estimation method provides an accurate power consumption estimation together with the maximum and minimum bounds； a maximum error of 8% against measurements for only 1.3% of the code studied is obtained for a MPEG decoder； other classical DSP applications are also presented.

We present SoftExplorer； a tool to estimate and analyze the power and energy consumption of an algorithm from the C program. The consumption of every loop is analyzed； and the influence of the data mapping is characterized. Several models of processor are available； from the simple RISC ARM7 to the very complex VLIW DSP TI-C67. Cache misses； pipeline stalls； and internal / external memory accesses are taken into account. We show how to analyze and optimize the power and energy consumption； and how to choose a processor and its operating frequency； for a MPEG-1 decoder. We also explain how to find the best data mapping for a DSP application.

We introduce a new approach to take into account the memory architecture and the memory mapping in high-level synthesis for data intensive applications. We formalize the memory mapping as a set of constraints for the synthesis, and defined a memory constraint graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping file to include those memory constraints in our HLS tool GAUT. It is possible, with the help of GAUT, to explore a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.

The acoustic echo cancellation with adaptive filters is a computationally intensive problem that needs real time cost effective solutions for embedded systems. Low Power optimized signal processing architectures are likely to provide such solutions in the future. In this paper； we present different realtime optimized architectures of the popular Gmdfα algorithm； obtained by a HLS CAD tool providing trade-off between area and power dissipation.

We introduce here a high level power estimation method； the power consumption of a whole algorithm is evaluated at a behavioral level instead of the classical study conducted at the instruction level. We present non exhaustive results on the energy models elaborated for a Texas Instruments DSP. This original energy estimation method has been applied to a classical algorithm (FIR) and validated by measurements； promising results provide an error of less than 8% .

It is now well admitted that interconnects introduce delays and consume power and chip resources. To deal with these problems, some studies have been done on performance optimization. However, as the results presented in this paper show, such techniques are not based on good criteria for interconnect performance optimizations. We have, therefore, developed a high-level estimation tool based on transistor-level characteristics, which provides fast and accurate figures for both time and power consumption. These results allowed us to create a new interconnect consumption model and also to determine new key issues that have to be taken into account for future performance optimizations.

A complete methodology to estimate power consumption at the C-level for off-the-shelf processors is proposed. It relies on the Functional-Level Power Analysis, which results in a power model of the processor； this model describes the consumption variations relatively to algorithmic and configuration parameters. Some parameters can be predicted directly from the C-algorithm with simple assumptions on the compilation. Estimation results are summarized on a consumption map； then the designer can check the algorithm with the application constraints. Maximum and minimum bounds are also provided. Applied to the TI C6x, the estimation method provides a maximum error of 6% against measurements for classical DSP algorithms.