An exclusion region of interest imaging overlay target includes a self- symmetric target structure including two or more pattern elements, and an additional target structure including two or more pattern elements, wherein each of pattern elements of the additional target structure is contained within a boundary defined by one of the pattern elements of the self-symmetric target structure, wherein the self -symmetric target structure is characterized by a composite exterior region of interest, wherein the composite exterior region of interest is formed by removing two or more exclusion zones corresponding with the pattern elements of the additional target structure from an exterior region of interest encompassing the self-symmetric target structure, wherein each of the pattern elements of the additional target structure is characterized by an interior region of interest, wherein the self-symmetric target structure and the additional target structure are configured to have a common center of symmetry upon alignment.

A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.

A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.

No abstract is available for this article.

No abstract is available for this article.