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Now showing items 1 - 8 of 8

  • The basic I-V characteristics of memristor model:simulation and analysis

    Rziga, Faten Ouaja   Mbarek, Khaoula   Ghedira, Sami   Besbes, Kamel  

    The memristor is fundamental electrical element theoretically postulated by Leon Chua in 1971 and successfully fabricated by HP Labs in 2008. However, its electrical characteristics are not yet fully understood which really leads us to study the behavior of such devices. For this development, it is essential to analyze a simple and flexible memristor model, for that reason SPICE memristor model seems to be frequently usable, especially in recent years, for its highly flexible and product very reliable and suitable for the electronic application. The adjustment of this model is based on the implementation of several parameters, which enables the changing on the I-V characteristics of the device. Our aim is to analyze the functioning behavior of memristive devices within different types of the input voltage to demonstrate the flexibility and reliability of our work model. Our simulation results have been committed to prove the basic I-V characteristics of such device, the switching behavior of this model for different applications (biological, neuromorphic...).
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  • An efficient Verilog-A memristor model implementation:simulation and application

    Rziga, Faten Ouaja   Mbarek, Khaoula   Ghedira, Sami   Besbes, Kamel  

    Complementary metal-oxide-semiconductor (CMOS) technology is reaching its limits due to the continuous shrinking process, which has an impact on various aspects including device size, performance, and power consumption. The memristor is one of the promising devices under investigation for use with deep-nanometer CMOS, having applicability in several fields due to its nonlinear behavior, nonvolatility, low power consumption, high density, and CMOS compatibility. Several models for memristors have been developed to date, but there is a requirement for compact models that are both flexible and sufficiently accurate. A general memristor model generated in Verilog-A is discussed herein to confirm its behavior in the one-transistor one-resistor (1T1R) oxide-based random-access memory (OxRAM) configuration, and validated at circuit level. The results of the model correlate well with experimental characterization data for the HfO2-based OxRAM memristor device, describing the characteristics of both its bipolar and unipolar memristor behaviors. The 1T1R structure is analyzed using the Spectre circuit simulator. Two cases are considered, using the cell as either programmable read-only memory (PROM) or electrically erasable programmable read-only memory (EEPROM). The simulation results confirm the desired nonlinear memristor characteristic, and the applicability of the model to fit and simulate different switching behaviors. The results are verified against both electrical and experimental characterization data, suggesting that the Verilog-A model is suitable for low-power and high-density logic circuit applications at the industrial level.
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  • Measurement and numerical analysis of C-V characteristics for normally-on SiCED-JFET

    Ghedira, Sami   Buttay, Cyril   Morel, Hervé   Besbes, Kamel  

    In this paper, terminal capacitances of a normally-on SiCED-JFET are measured, analyzed and simulated. All these capacitances are measured using an auto-balanced (guarded) capacitance test-bench that leads to the standard 3-terminal model capacitors C-GS, C-DS and C-GD. This test bench is developed to measure each capacitance individually, without any mutual influence. 2D finite-element simulations are used to show that the capacitance C-GD cannot be modeled by a standard planar junction model. This is due to the influence of two dimensional effects around the buried layer P+. A new analytical model of C-GD is proposed. A good agreement is obtained between simulations and measurements of the different capacitances.
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  • Measurement and numerical analysis of C-V characteristics for normally-on SiCED-JFET

    Ghedira, Sami   Buttay, Cyril   Morel, Herve   Besbes, Kamel  

    In this paper, terminal capacitances of a normally-on SiCED-JFET are measured, analyzed and simulated. All these capacitances are measured using an auto-balanced (guarded) capacitance test-bench that leads to the standard 3-terminal model capacitors C-GS, C-DS and C-GD. This test bench is developed to measure each capacitance individually, without any mutual influence. 2D finite-element simulations are used to show that the capacitance C-GD cannot be modeled by a standard planar junction model. This is due to the influence of two dimensional effects around the buried layer P+. A new analytical model of C-GD is proposed. A good agreement is obtained between simulations and measurements of the different capacitances.
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  • On the design and analysis of a compact array with 1T1R RRAM memory element

    Mbarek, Khaoula   Rziga, Faten Ouaja   Ghedira, Sami   Besbes, Kamel  

    In this paper, an analysis of a Verilog-A memristor model is discussed in order to be implemented in a 1T1R cell by exploring the characterization data of an OxRRAM device. The proposed analysis is done using mathematical formulation and verified by Spectre circuit simulator. The analysis is tested for a digital logic gate such as NAND gate for both, SET and RESET processes to perform read and write operations. Moreover, we explore diverse types of memory cells, two configurations are considered as a PROM and an EEPROM. Additionally, the implementation of the Verilog-A model on a crossbar array is discussed in details in terms of switching speed and the range of resistance. A comparison between the performances of various existing memory cells is also discussed. Our simulation results carry the desired nonlinear memristor fingerprint, the applicability to fit different switching behaviors. These results are verified by both electrical and experimental characterization data. We conclude that the proposed Verilog-A model is suitable for digitals circuits, crossbar arrays, low-power and high-density applications at the industrial levels.
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  • A novel approach to extract accurate design parameters of PiN diode

    Ben Salah, Tarek   Ghedira, Sami   Garrab, Hatem   Morel, Herve   Riseletto, Damien   Besbes, Kamel  

    Accurate modelling of PiN diode transient behaviour is necessary to extract design parameters which are not documented in datasheets. To meet this requirement, this paper introduces a novel approach giving the possibility to identify accurate parameters of a given device. The used technique is based only on two stages. First, the design parameters are initialized and optimized. Second, they are refined by minimizing the cost function which depends on the transient switching parameters (I-RM, V-RM and t(rr)). With a simple and CPU time-saving approach this technique leads to extract design parameters without necessarily knowing the exact technological architecture of the PiN diode. Moreover, in order to validate the proposed approach and the parameter extraction procedure three commercial diodes are tested. A good agreement between experimental and simulation data is obtained. Copyright (C) 2007 John Wiley & Sons, Ltd.
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  • A novel design approach for the epitaxial layer for 4H-SiC and 6H-SiC power bipolar devices

    Ben Salah, Tarek   Garrab, Hatem   Ghedira, Sami   Allard, Bruno   Risaletto, Damien   Raynaud, Christophe   Besbes, Kamel   Morel, Herve  

    The paper evaluates the optimal design of the low-doped base region inside power diodes and other bipolar devices. It is demonstrated theoretically that a low-doped base region of P+N-N+ diodes can provide a high breakdown voltage and an optimal on-resistance R-on. A simple, accurate and CPU timesaving approach is presented to extract an optimal value for the base region width, W-B. and its doping concentration, N-D. The paper details an analytical relation between W-B and N-D, and gives a method for quantifying the trade-off between their values for a given breakdown voltage and for obtaining the minimal on-resistance. Analytical results are confronted with experimental results for 4H-SiC- and 6H-SiC-based diodes. (c) 2006 Elsevier Ltd. All rights reserved.
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  • [IEEE 2017 International Conference on Engineering & MIS (ICEMIS) - Monastir, Tunisia (2017.5.8-2017.5.10)] 2017 International Conference on Engineering & MIS (ICEMIS) - Dynamical resistive switching of a generic memristor model: Analysis and simulation

    Ghedira, Sami   Rziga, Faten Ouaja   Mbarek, Khaoula   Besbes, Kamel  

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