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The Study of How to Reduce ILD Loss in High-k and Metal Gate Last Process

Author:
Zhao, J.   Gao, H. J.   Zeng, Y. Z.   Awut, K.   Song, W. J.   Yu, S. F.   Cai, G.   Zhang, B.  


Journal:
ECS Transactions


Issue Date:
2014


Abstract(summary):

High-k last and metal gate last process becomes the main stream in 20nm and beyond technology. In high-k last process, the thermal dummy gate oxide (DGO) must be removed before the growth of interfacial layer (IL). In conventional process, to avoid the plasma damage to the device, wet etch is the most popular process to remove DGO. Because the etch rate of ILD(inter layer dielectric) oxide and CESL(CT etch stop layer) layers is much higher than thermal oxide, during the removal of DGO, serious ILD and CESL loss is observed, which will induce many of following process issues, such as high-k/metal residue, gate height variation, work function shift, etc. In this paper, multi-methods are studied to reduce the loss of ILD and CESL layer. The study mainly includes improvements on film quality and optimization of removal process. Finally, the selectivity of ILD oxide and CESL to thermal dummy gate oxide can reach ~1:1.


Page:
721-725


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