Parallel architecture for real-time video communication

Journal:

Proceedings of the SPIE - The International Society for Optical Engineering

Issue Date:

1990

Abstract(summary):

A video codec is described, based on several parallel digital signal processors which can be easily programmed to implement the H.261 algorithm and are organized as a single-instruction multiple-data computing architecture. Both the encoder and the decoder divide a picture in regions of horizontal strips and use one local processor per region. These local processors code (decode) one horizontal strip of data which, using the terminology of the H.261 standard, corresponds to two groups of blocks. They also communicate to a central processor which multiplexes (demultiplexes) the coded data from (for) the processors in the encoder (decoder). Lateral communication between adjacent processors is implemented to allow comparisons between blocks situated in neighbouring regions, as required by most motion estimation algorithms

Page:

380---387387